SN74AUC2G08 GATE Datasheet

SN74AUC2G08 Datasheet, PDF, Equivalent


Part Number

SN74AUC2G08

Description

DUAL 2-INPUT POSITIVE-AND GATE

Manufacture

etcTI

Total Page 17 Pages
Datasheet
Download SN74AUC2G08 Datasheet


SN74AUC2G08
www.ti.com
SN74AUC2G08
DUAL 2-INPUT POSITIVE-AND GATE
SCES477C – AUGUST 2003 – REVISED JANUARY 2007
FEATURES
Available in the Texas Instruments
NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 1.5 ns at 1.8 V
Low Power Consumption, 10-µA at 1.8 V
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCT PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
1A 1
1B 2
2Y 3
8 VCC
7 1Y
6 2B
1A
1B
2Y
GND
1
2
3
4
8 VCC
7 1Y
6 2B
5 2A
GND 4 5 2A
2Y 3 6 2B
1B 2 7 1Y
1A 1 8 VCC
GND
4
5 2A
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This dual 2-input positive-AND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to
1.95-V VCC operation.
The SN74AUC2G08 performs the Boolean function A B or Y = A + B in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of
Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.
ORDERING INFORMATION
TA
–40°C to 85°C
PACKAGE (1)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SSOP – DCT
Reel of 3000
Reel of 3000
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
SN74AUC2G08YZPR
_ _ _UE_
SN74AUC2G08DCTR
U08_ _ _
VSSOP – DCU
Reel of 3000
SN74AUC2G08DCUR
U08_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated

SN74AUC2G08
SN74AUC2G08
DUAL 2-INPUT POSITIVE-AND GATE
SCES477C – AUGUST 2003 – REVISED JANUARY 2007
FUNCTION TABLE
(each gate)
INPUTS
CLK
D
HH
LX
XL
OUTPUT
Y
H
L
L
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1A
2
1B
7
1Y
5
2A
6
2B
3
2Y
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Output voltage range(2)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
Continuous current through VCC or GND
DCT package
θJA Package thermal impedance(3)
DCU package
YZP package
Tstg Storage temperature range
MIN
–0.5
–0.5
–0.5
–0.5
–65
MAX
3.6
3.6
3.6
VCC + 0.5
–50
–50
±20
±100
220
227
102
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
2 Submit Documentation Feedback


Features www.ti.com SN74AUC2G08 DUAL 2-INPUT POS ITIVE-AND GATE SCES477C – AUGUST 2003 – REVISED JANUARY 2007 FEATURES Available in the Texas Instruments Na noFree™ Package • Optimized for 1.8 -V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation • Ioff Supports Partial-Power-Down Mo de Operation • Sub-1-V Operable • M ax tpd of 1.5 ns at 1.8 V • Low Powe r Consumption, 10-µA at 1.8 V • ±8- mA Output Drive at 1.8 V • Latch-Up P erformance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JES D 22 – 2000-V Human-Body Model (A114- A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DC T PACKAGE (TOP VIEW) DCU PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) 1A 1 1B 2 2Y 3 8 VCC 7 1Y 6 2B 1A 1B 2Y GN D 1 2 3 4 8 VCC 7 1Y 6 2B 5 2A GND 4 5 2A 2Y 3 6 2B 1B 2 7 1Y 1A 1 8 VCC G ND 4 5 2A See mechanical drawings fo r dimensions. DESCRIPTION/ORDERING INF ORMATION This dual 2-input positive-AND gate is operational at 0.8-V to 2.7-V VCC, but is desig.
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