SN74AUC2G125 GATE Datasheet

SN74AUC2G125 Datasheet, PDF, Equivalent


Part Number

SN74AUC2G125

Description

DUAL BUS BUFFER GATE

Manufacture

etcTI

Total Page 18 Pages
Datasheet
Download SN74AUC2G125 Datasheet


SN74AUC2G125
www.ti.com
SN74AUC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES532D – DECEMBER 2003 – REVISED AUGUST 2007
FEATURES
Available in the Texas Instruments
NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 1.8 ns at 1.8 V
Low Power Consumption, 10 μA at 1.8 V
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCT PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
1OE
1A
2Y
1
2
3
8 VCC
7 2OE
6 1Y
1OE
1A
2Y
GND
1
2
3
4
8 VCC
7 2OE
6 1Y
5 2A
GND 4 5 2A
2Y 3 6 1Y
1A 2 7 2OE
1OE 1 8 VCC
GND
4
5 2A
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This dual bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V
VCC operation.
The SN74AUC2G125 features dual line drivers with 3-state outputs. The outputs are disabled when the
associated output-enable (OE) input is high.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
TA
–40°C to 85°C
ORDERING INFORMATION
PACKAGE (1) (2)
ORDERABLE PART NUMBER
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74AUC2G125YZPR
SSOP – DCT
Reel of 3000 SN74AUC2G125DCTR
VSSOP – DCU
Reel of 3000 SN74AUC2G125DCUR
TOP-SIDE MARKING(3)
_ _ _UM_
U25_ _ _
U25_
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated

SN74AUC2G125
SN74AUC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES532D – DECEMBER 2003 – REVISED AUGUST 2007
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of
Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OE A
LH
LL
HX
OUTPUT
Y
H
L
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1OE
2
1A
6
1Y
7
2OE
5
2A
3
2Y
2 Submit Documentation Feedback


Features www.ti.com SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES532D – DECEMBER 2003 – REVISED AUGUST 2007 FEATURES • Available in the Texas I nstruments NanoFree™ Package • Opti mized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Sign al Operation • Ioff Supports Partial- Power-Down Mode Operation • Sub-1-V O perable • Max tpd of 1.8 ns at 1.8 V • Low Power Consumption, 10 μA at 1 .8 V • ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protectio n Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Mod el (C101) DCT PACKAGE (TOP VIEW) DCU PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) 1OE 1A 2Y 1 2 3 8 VCC 7 2OE 6 1Y 1OE 1A 2Y GND 1 2 3 4 8 VCC 7 2O E 6 1Y 5 2A GND 4 5 2A 2Y 3 6 1Y 1A 2 7 2OE 1OE 1 8 VCC GND 4 5 2A See me chanical drawings for dimensions. DESC RIPTION/ORDERING INFORMATION This dual bus buffer gate is operational at 0.8-V to 2.7-V VCC, bu.
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