SN74AUC2G240 BUFFER/DRIVER Datasheet

SN74AUC2G240 Datasheet, PDF, Equivalent


Part Number

SN74AUC2G240

Description

DUAL BUFFER/DRIVER

Manufacture

etcTI

Total Page 17 Pages
Datasheet
Download SN74AUC2G240 Datasheet


SN74AUC2G240
www.ti.com
SN74AUC2G240
DUAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES534C – DECEMBER 2003 – REVISED JANUARY 2007
FEATURES
Available in the Texas Instruments
NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 1.8 ns at 1.8 V
Low Power Consumption, 10 µA at 1.8 V
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCT PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
1OE
1A
2Y
1
2
3
8 VCC
7 2OE
6 1Y
1OE
1A
2Y
GND
1
2
3
4
8 VCC
7 2OE
6 1Y
5 2A
GND 4 5 2A
2Y 3 6 1Y
1A 2 7 2OE
1OE 1 8 VCC
GND
4
5 2A
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This dual buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC
operation.
The SN74AUC2G240 is designed specifically to improve the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
This device is organized as two 1-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low,
the device passes data from the A input to the Y output. When OE is high, the outputs are in the
high-impedance state.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
–40°C to 85°C
PACKAGE (1)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SSOP – DCT
Reel of 3000
Reel of 3000
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
SN74AUC2G240YZPR
_ _ _UK_
SN74AUC2G240DCTR
U40_ _ _
VSSOP – DCU
Reel of 3000
SN74AUC2G240DCUR
UK_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated

SN74AUC2G240
SN74AUC2G240
DUAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES534C – DECEMBER 2003 – REVISED JANUARY 2007
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of
Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OE A
LH
LL
HX
OUTPUT
Y
L
H
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1OE
2
1A
6
1Y
7
2OE
5
2A
3
2Y
2 Submit Documentation Feedback


Features www.ti.com SN74AUC2G240 DUAL BUFFER/DRI VER WITH 3-STATE OUTPUTS SCES534C – D ECEMBER 2003 – REVISED JANUARY 2007 FEATURES • Available in the Texas In struments NanoFree™ Package • Optim ized for 1.8-V Operation and Is 3.6-V I /O Tolerant to Support Mixed-Mode Signa l Operation • Ioff Supports Partial-P ower-Down Mode Operation • Sub-1-V Op erable • Max tpd of 1.8 ns at 1.8 V • Low Power Consumption, 10 µA at 1. 8 V • ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA P er JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Mode l (C101) DCT PACKAGE (TOP VIEW) DCU P ACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) 1OE 1A 2Y 1 2 3 8 VCC 7 2OE 6 1Y 1OE 1A 2Y GND 1 2 3 4 8 VCC 7 2OE 6 1Y 5 2A GND 4 5 2A 2Y 3 6 1Y 1A 2 7 2OE 1OE 1 8 VCC GND 4 5 2A See mec hanical drawings for dimensions. DESCR IPTION/ORDERING INFORMATION This dual buffer/driver is operational at 0.8-V to 2.7-V VCC, but i.
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