SN74AUC2G80 FLIP-FLOP Datasheet

SN74AUC2G80 Datasheet, PDF, Equivalent


Part Number

SN74AUC2G80

Description

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

Manufacture

etcTI

Total Page 17 Pages
Datasheet
Download SN74AUC2G80 Datasheet


SN74AUC2G80
www.ti.com
SN74AUC2G80
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES540C – JANUARY 2004 – REVISED JANUARY 2007
FEATURES
Available in the Texas Instruments
NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 1.9 ns at 1.8 V
DCT PACKAGE
(TOP VIEW)
Low Power Consumption, 10-µA Max ICC
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCU PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
1CLK
1D
2Q
1
2
3
8 VCC
7 1Q
6 2D
1CLK
1D
2Q
GND
1
2
3
4
8 VCC
7 1Q
6 2D
5 2CLK
GND 4 5 2CLK
2Q 3 6 2D
1D 2 7 1Q
1CLK 1 8 VCC
GND
4
5 2CLK
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically
for 1.65-V to 1.95-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the
rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without
affecting the levels at the outputs.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
–40°C to 85°C
PACKAGE (1)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SSOP – DCT
Reel of 3000
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
SN74AUC2G80YZPR
_ _ _UX_
SN74AUC2G80DCTR
U80_ _ _
VSSOP – DCU
Reel of 3000 SN74AUC2G80DCUR
UX_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated

SN74AUC2G80
SN74AUC2G80
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES540C – JANUARY 2004 – REVISED JANUARY 2007
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
CLK
D
H
L
LX
OUTPUT
Q
L
H
Q0
LOGIC DIAGRAM (POSITIVE LOGIC)
CLK
CC
C
TG
C
D TG
C
TG
C
C
TG
www.ti.com
Q
CC
C
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Output voltage range(2)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
Continuous current through VCC or GND
DCT package
θJA Package thermal impedance(3)
DCU package
YZP package
Tstg Storage temperature range
MIN
–0.5
–0.5
–0.5
–0.5
–65
MAX
3.6
3.6
3.6
VCC + 0.5
–50
–50
±20
±100
220
227
102
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
2 Submit Documentation Feedback


Features www.ti.com SN74AUC2G80 DUAL POSITIVE-ED GE-TRIGGERED D-TYPE FLIP-FLOP SCES540C – JANUARY 2004 – REVISED JANUARY 20 07 FEATURES • Available in the Texa s Instruments NanoFree™ Package • O ptimized for 1.8-V Operation and Is 3.6 -V I/O Tolerant to Support Mixed-Mode S ignal Operation • Ioff Supports Parti al-Power-Down Mode Operation • Sub-1- V Operable • Max tpd of 1.9 ns at 1.8 V DCT PACKAGE (TOP VIEW) • Low Powe r Consumption, 10-µA Max ICC • ±8-m A Output Drive at 1.8 V • Latch-Up Pe rformance Exceeds 100 mA Per JESD 78, C lass II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A ) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DCU PACKAGE (TOP VIEW) YZP PACKAGE (BOTTO M VIEW) 1CLK 1D 2Q 1 2 3 8 VCC 7 1Q 6 2D 1CLK 1D 2Q GND 1 2 3 4 8 VCC 7 1Q 6 2D 5 2CLK GND 4 5 2CLK 2Q 3 6 2D 1D 2 7 1Q 1CLK 1 8 VCC GND 4 5 2CLK See mechanical drawings for dimensions . DESCRIPTION/ORDERING INFORMATION This dual positive-edge-triggered D-type flip-flop is opera.
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