SN74AUC2GU04 GATE Datasheet

SN74AUC2GU04 Datasheet, PDF, Equivalent


Part Number

SN74AUC2GU04

Description

DUAL INVERTER GATE

Manufacture

etcTI

Total Page 15 Pages
Datasheet
Download SN74AUC2GU04 Datasheet


SN74AUC2GU04
www.ti.com
SN74AUC2GU04
DUAL INVERTER GATE
SCES438C – APRIL 2003 – REVISED JANUARY 2007
FEATURES
Available in the Texas Instruments
NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Sub-1-V Operable
Unbuffered Outputs
Max tpd of 1.9 ns at 1.8 V
Low Power Consumption, 10 µA at 1.8 V
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
1A
GND
1
2
6 1Y
1A 1 6 1Y
GND 2 5 VCC
5 VCC 2A 3 4 2Y
YZP PACKAGE
(BOTTOM VIEW)
2A 3 4 2Y
GND 2 5 VCC
1A 1 6 1Y
2A 3 4 2Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This dual inverter is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC
operation.
The SN74AUC2GU04 contains two inverters with unbuffered outputs and performs the Boolean function Y = A.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of
Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.
TA
–40°C to 85°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
Reel of 3000 SN74AUC2GU04YZPR
SOT (SOT-23) – DBV
Reel of 3000 SN74AUC2GU04DBVR
SOT (SC-70) – DCK
Reel of 3000 SN74AUC2GU04DCKR
TOP-SIDE MARKING(2)
_ _ _UD_
UU4_
UD_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated

SN74AUC2GU04
SN74AUC2GU04
DUAL INVERTER GATE
SCES438C – APRIL 2003 – REVISED JANUARY 2007
FUNCTION TABLE
(EACH INVERTER)
INPUT
A
H
L
OUTPUT
Y
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1A
6
1Y
3
2A
4
2Y
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI Input voltage range(2)
VO Output voltage range(2)
IIK Input clamp current
IOK Output clamp current
IO Continuous output current
Continuous current through VCC or GND
θJA Package thermal impedance(3)
Tstg Storage temperature range
VI < 0
VO < 0
DBV package
DCK package
YZP package
MIN
–0.5
–0.5
–0.5
–65
MAX
3.6
3.6
VCC + 0.5
–50
–50
±20
±100
165
259
123
150
UNIT
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
2 Submit Documentation Feedback


Features www.ti.com SN74AUC2GU04 DUAL INVERTER G ATE SCES438C – APRIL 2003 – REVISED JANUARY 2007 FEATURES • Available i n the Texas Instruments NanoFree™ Pac kage • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mi xed-Mode Signal Operation • Sub-1-V O perable • Unbuffered Outputs • Max tpd of 1.9 ns at 1.8 V • Low Power C onsumption, 10 µA at 1.8 V • ±8-mA Output Drive at 1.8 V • Latch-Up Perf ormance Exceeds 100 mA Per JESD 78, Cla ss II • ESD Protection Exceeds JESD 2 2 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 10 00-V Charged-Device Model (C101) DBV P ACKAGE (TOP VIEW) DCK PACKAGE (TOP VIE W) 1A GND 1 2 6 1Y 1A 1 6 1Y GND 2 5 VCC 5 VCC 2A 3 4 2Y YZP PACKAGE (B OTTOM VIEW) 2A 3 4 2Y GND 2 5 VCC 1A 1 6 1Y 2A 3 4 2Y See mechanical drawing s for dimensions. DESCRIPTION/ORDERING INFORMATION This dual inverter is oper ational at 0.8-V to 2.7-V VCC, but is d esigned specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2GU04 contains two inverter.
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