SN74AUC240 BUFFER/DRIVER Datasheet

SN74AUC240 Datasheet, PDF, Equivalent


Part Number

SN74AUC240

Description

OCTAL BUFFER/DRIVER

Manufacture

etcTI

Total Page 15 Pages
Datasheet
Download SN74AUC240 Datasheet


SN74AUC240
D Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
D Ioff Supports Partial-Power-Down Mode
Operation
D Sub 1-V Operable
D Max tpd of 1.7 ns at 1.8 V
D Low Power Consumption, 20-µA Max ICC
D ±8-mA Output Drive at 1.8 V
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN74AUC240
OCTAL BUFFER/DRIVER
WITH 3ĆSTATE OUTPUTS
SCES430A − MARCH 2003 − REVISED MARCH 2003
RGY PACKAGE
(TOP VIEW)
1A1 2
2Y4 3
1A2 4
2Y3 5
1A3 6
2Y2 7
1A4 8
2Y1 9
1
10
20
19 2OE
18 1Y1
17 2A4
16 1Y2
15 2A3
14 1Y3
13 2A2
12 1Y4
11
description/ordering information
This octal buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC
operation.
The SN74AUC240 is designed specifically to improve the performance and density of 3-state memory address
drivers, clock drivers, and bus-oriented receivers and transmitters.
This device is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low,
the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C QFN − RGY
Tape and reel SN74AUC240RGYR
MS240
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
1

SN74AUC240
SN74AUC240
OCTAL BUFFER/DRIVER
WITH 3ĆSTATE OUTPUTS
SCES430A − MARCH 2003 − REVISED MARCH 2003
logic diagram (positive logic)
1
1OE
2
1A1
FUNCTION TABLE
(each 4-bit buffer/driver)
INPUTS
OE A
OUTPUT
Y
LH
L
LL
H
HX
Z
18
1Y1
19
2OE
11
2A1
9
2Y1
1A2 4
16 1Y2
2A2 13
7 2Y2
6
1A3
14 1Y3
15
2A3
5 2Y3
8
1A4
12 1Y4
17
2A4
3 2Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-5.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features D Optimized for 1.8-V Operation and is 3 .6-V I/O Tolerant to Support Mixed-Mode Signal Operation D Ioff Supports Parti al-Power-Down Mode Operation D Sub 1-V Operable D Max tpd of 1.7 ns at 1.8 V D Low Power Consumption, 20-µA Max ICC D ±8-mA Output Drive at 1.8 V D Latch- Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds J ESD 22 − 2000-V Human-Body Model (A11 4-A) − 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) GND 2A1 SN74AUC240 OCTAL BUFFER/DRIVER WITH 3ĆSTATE OUTPUTS SCES430A − MAR CH 2003 − REVISED MARCH 2003 RGY PACK AGE (TOP VIEW) 1OE VCC 1A1 2 2Y4 3 1A 2 4 2Y3 5 1A3 6 2Y2 7 1A4 8 2Y1 9 1 10 20 19 2OE 18 1Y1 17 2A4 16 1Y2 15 2A3 14 1Y3 13 2A2 12 1Y4 11 description/o rdering information This octal buffer/d river is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1 .65-V to 1.95-V VCC operation. The SN74 AUC240 is designed specifically to impr ove the performance and density of 3-state memory address drivers, clock dri.
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