TAS5825M Amplifier Datasheet

TAS5825M Datasheet, PDF, Equivalent


Part Number

TAS5825M

Description

Closed-Loop Class-D Audio Amplifier

Manufacture

etcTI

Total Page 30 Pages
Datasheet
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TAS5825M
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TAS5825M
SLASEH7F – OCTOBER 2019 – REVISED NOVEMBER 2019
TAS5825M 4.5 V to 26.4 V, 38-W Stereo, Inductor-Less, Digital Input, Closed-Loop Class-D
Audio Amplifier with 192-kHz Extended Audio Processing
1 Features
1 Flexible audio I/O:
– Supports 32, 44.1, 48, 88.2, 96, 192 kHz
sample rates
– I2S, LJ, RJ, TDM, SDOUT for audio
monitoring, sub-channel or echo cancellation
– Supports 3-wire digital audio interface (no
MCLK required)
• High-efficiency class-Dlration
– > 90% Power efficiency, 90 mΩ RDSon
– Low quiescent current, <20 mA at PVDD=12V
• Supports multiple output configurations
– 1 × 53 W, 1.0 Mode (4-Ω, 22V, THD+N=1%)
– 1 × 65 W, 1.0 Mode (4-Ω, 22V, THD+N=10%)
– 2 × 30 W, 2.0 Mode (8-Ω, 24 V, THD+N=1%)
– 2 × 38 W, 2.0 Mode (8-Ω, 24 V, THD+N=10%)
• Excellent audio performance:
– THD+N 0.03% at 1 W, 1 kHz, PVDD = 12 V
– SNR 110 dB (A-weighted), ICN 35 µVRMS
• Flexible processing features
– 3-Band advanced DRC + AGL2 × 15 BQs,
– Sound field spatializer (SFS), level meter
– 96-kHz, 192-kHz processor sampling
– Dynamic EQ, Bass enhancement and speaker
thermal/excursion protection
• Flexible power supply configurations
– PVDD: 4.5 V to 26.4 V
– DVDD and I/O: 1.8 V or 3.3 V
• Excellent Integrated self-protection:
– Over-current error (OCE)
– Cycle-by-cycle current limit
– Over-temperature warning (OTW)
– Over-temperature error (OTE)
– Under and over-voltage lock-out
(UVLO/OVLO)
• Easy system integration
– I2C Software control
– Reduced solution size
– Small 5 x 5 mm Package
– Fewer passives required compared to
open-loop devices
– No bulky electrolytic capacitors or large
inductors required for most applications
1
2 Applications
DTV, HDTV, UHD and multi-purpose monitors
• Soundbars and subwoofers, notebooks, pc
speakers
Wireless, bluetooth speakers
Smart speakers (with voice assistant)
3 Description
The TAS5825M is a stereo high-performance closed-
loop Class-D with integrated audio processor with up
to 192-kHz architecture.
The powerful audio DSP core supports several
advanced audio process flows. With 48-kHz or 96-
kHz architecture, an integrated SRC (Sample rate
convertor) detects the input sample rate change.
Then auto converts to the target sample rate which
DSP is running to avoid any audio artifacts. These
process flows support: 2×15 BQs, 3-Band DRC, Full-
band AGL (Automatic Gain Limiter), Smart Amplifier
Algorithm (Thermal and Excursion Protection), Bass
enhancement, Spatializer,THD manager, PVDD
Tracking and Thermal Foldback. The 192-kHz
process flow offers Full-band AGL and Thermal
Foldback .
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TAS5825M
VQFN (32) RHB 5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Speaker
L Channel
Speaker
R Channel
System
Processor
Digital
Audio
Source
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TAS5825M
TAS5825M
SLASEH7F – OCTOBER 2019 – REVISED NOVEMBER 2019
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information .................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements ................................................ 9
7.7 Typical Characteristics ............................................ 10
8 Parameter Measurement Information ................ 25
9 Detailed Description ............................................ 26
9.1 Overview ................................................................. 26
9.2 Functional Block Diagram ....................................... 26
9.3 Feature Description................................................. 27
9.4 Device Functional Modes........................................ 33
9.5 Programming and Control ....................................... 38
9.6 Register Maps ......................................................... 43
10 Application and Implementation........................ 81
10.1 Application Information.......................................... 81
10.2 Typical Applications ............................................. 83
11 Power Supply Recommendations ..................... 89
11.1 DVDD Supply ........................................................ 89
11.2 PVDD Supply ........................................................ 90
12 Layout................................................................... 91
12.1 Layout Guidelines ................................................. 91
12.2 Layout Example .................................................... 93
13 Device and Documentation Support ................. 95
13.1 Device Support...................................................... 95
13.2 Receiving Notification of Documentation Updates 95
13.3 Community Resources.......................................... 96
13.4 Trademarks ........................................................... 96
13.5 Electrostatic Discharge Caution ............................ 96
13.6 Glossary ................................................................ 96
14 Mechanical, Packaging, and Orderable
Information ........................................................... 96
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (October 2019) to Revision F
Page
• Formatted the front page to fit the Features and Applications onto one column .................................................................. 1
Changes from Revision D (December 2018) to Revision E
Page
• Added section: Class D Loop Bandwidth and Switching Frequency Setting ....................................................................... 32
• Added NOTE to the Overcurrent Limit (Cycle-By-Cycle) section ......................................................................................... 42
• Added register: SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]................................................................................... 53
• Changed capacitor values of C6, C9, C10, and C13 from 0.22 µF to 0.47 µF in Figure 152 ............................................. 83
Changes from Revision C (September 2018) to Revision D
Page
• Added the Thermal Foldback section ................................................................................................................................... 35
• Added Figure 93 .................................................................................................................................................................. 41
• Added Figure 94 .................................................................................................................................................................. 42
• Changed the Inductor Selections section ............................................................................................................................. 81
Changes from Revision B (August 2018) to Revision C
Page
• Deleted 001: 260K from Table 9 ......................................................................................................................................... 46
Changes from Revision A (June 2018) to Revision B
Page
• Changed the device status From: Advanced Information To: Production data ..................................................................... 1
2 Submit Documentation Feedback
Product Folder Links: TAS5825M
Copyright © 2019, Texas Instruments Incorporated


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity TAS5825M SLASEH7F – OCTOBER 2 019 – REVISED NOVEMBER 2019 TAS5825M 4.5 V to 26.4 V, 38-W Stereo, Inductor- Less, Digital Input, Closed-Loop Class- D Audio Amplifier with 192-kHz Extended Audio Processing 1 Features •1 Flex ible audio I/O: – Supports 32, 44.1, 48, 88.2, 96, 192 kHz sample rates – I2S, LJ, RJ, TDM, SDOUT for audio monit oring, sub-channel or echo cancellation – Supports 3-wire digital audio inte rface (no MCLK required) • High-effic iency class-Dlration – > 90% Power ef ficiency, 90 mΩ RDSon – Low quiescen t current, <20 mA at PVDD=12V • Suppo rts multiple output configurations – 1 × 53 W, 1.0 Mode (4-Ω, 22V, THD+N=1 %) – 1 × 65 W, 1.0 Mode (4-Ω, 22V, THD+N=10%) – 2 × 30 W, 2.0 Mode (8- , 24 V, THD+N=1%) – 2 × 38 W, 2.0 M ode (8-Ω, 24 V, THD+N=10%) • Excelle nt audio performance: – THD+N ≤ 0.0 3% at 1 W, 1 kHz, PVDD = 12 V – SNR ≥ 110 dB (A-weighted), ICN ≤ 35 µVRMS • Flexible processing features –.
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