TAS5805M Amplifier Datasheet

TAS5805M Datasheet, PDF, Equivalent


Part Number

TAS5805M

Description

Closed-Loop Class-D Audio Amplifier

Manufacture

etcTI

Total Page 30 Pages
Datasheet
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TAS5805M
SLASEH5C – MAY 2018 – REVISED DECEMBER 2018
TAS5805M 23-W, Inductor-Less, Digital Input, Stereo, Closed-Loop Class-D Audio
Amplifier with Enhanced Processing and Low Power Dissipation
1 Features
1 Supports Multiple Output Configurations
– 2 × 23 W in 2.0 Mode (8-Ω, 21 V, THD+N=1%)
– 45 W in Mono Mode (4-Ω, 21 V, THD+N=1%)
• Excellent Audio Performance
– THD+N 0.03% at 1 W, 1 kHz, PVDD = 12 V
– SNR 107 dB (A-weighted), Noise Level < 40
µVRMS
• Low Quiescent Current with Hybrid Modulation
– 16.5 mA at PVDD = 13.5 V , 22 µH + 0.68 µF
Filter
• Flexible Power Supply Configurations
– PVDD: 4.5 V to 26.4 V
– DVDD and I/O: 1.8 V or 3.3 V
• Flexible Audio I/O
– I2S, LJ, RJ, TDM, 3-Wire Digital Audio
Interface (No MCLK Required)
– Supports 32, 44.1, 48, 88.2, 96 kHz Sample
Rates
– SDOUT for Audio Monitoring, Sub-Channel or
Echo Cancellation
• Enhanced Audio Processing
– Multi-Band Advanced DRC and AGL
– 2×15 BQs, Thermal Foldback, DC Blocking
– Input Mixer, Output Crossbar, Level Meter
– 5 BQs + 1 Band DRC +THD Manager for the
Subwoofer Channel
– Sound Field Spatializer option
• Integrated Self-Protection
– Adjacent Pin to Pin Short Without Damage
– Over-Current Error (OCE)
– Over-Temperature Warning (OTW)
– Over-Temperature Error (OTE)
– Under/Over-Voltage Lock-out (UVLO/OVLO)
• Easy System Integration
– I2C Software Control
– Reduced Solution Size
– Fewer Passives Required Compared to
Open-Loop Devices
– Inductor-less Operation (Ferrite Bead) for
most cases where PVDD 14V
2 Applications
• LCD TV, OLED TV
• Wireless Speaker, Smart Speaker with Voice
Assistant
• Soundbar, Wired Speaker , Bookshelf Stereo
System
• Desktop PC, Notebook PC
• AV Receiver, Smart Home and IoT Appliance
3 Description
The TAS5805M is a high-efficiency, stereo, closed-
loop Class-D amplifier offering a cost-effective digital-
input solution with low power dissipation and sound
enrichment. The device’s integrated audio processor
and 96 kHz architecture support advanced audio
process flow, including SRC, 15 BQs per channel,
volume control, audio mixing, 3-band 4th order DRC,
full-band AGL, THD manager and level meter.
Featuring TI's proprietary Hybrid Modulation scheme,
the TAS5805M consumes very-low quiescent current
(16.5 mA at 13.5 V PVDD), extending battery life in
portable audio applications. With advanced EMI
suppression technology, designers can leverage
inexpensive ferrite bead filters to reduce board space
and system cost.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TAS5805M
TSSOP (28) PWP 9.7 mm × 4.4 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
Speaker
L Channel
Speaker
R Channel
DVDD
System
Processor
Digital
Audio
Source
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TAS5805M
TAS5805M
SLASEH5C – MAY 2018 – REVISED DECEMBER 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information .................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements ............................................... 9
7.7 Typical Characteristics ............................................ 10
8 Parameter Measurement Information ................ 25
9 Detailed Description ............................................ 27
9.1 Overview ................................................................. 27
9.2 Functional Block Diagram ....................................... 27
9.3 Feature Description................................................. 28
9.4 Device Functional Modes........................................ 34
9.5 Programming and Control ....................................... 39
9.6 Register Maps ......................................................... 45
10 Application and Implementation........................ 76
10.1 Application Information.......................................... 76
10.2 Typical Applications ............................................. 78
11 Power Supply Recommendations ..................... 86
11.1 DVDD Supply ........................................................ 86
11.2 PVDD Supply ........................................................ 86
12 Layout................................................................... 88
12.1 Layout Guidelines ................................................. 88
12.2 Layout Example .................................................... 90
13 Device and Documentation Support ................. 91
13.1 Device Support...................................................... 91
13.2 Receiving Notification of Documentation Updates 91
13.3 Community Resources.......................................... 92
13.4 Trademarks ........................................................... 92
13.5 Electrostatic Discharge Caution ............................ 92
13.6 Glossary ................................................................ 92
14 Mechanical, Packaging, and Orderable
Information ........................................................... 92
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October 2018) to Revision C
Page
• Added Figure 97 .................................................................................................................................................................. 43
• Added Figure 98 .................................................................................................................................................................. 43
Changes from Revision A (July 2018) to Revision B
Page
• Changed From: (<16.5 mA at 13.5 V PVDD) To:(16.5 mA at 13.5 V PVDD) in the Description ........................................... 1
• Changed the Typical Characteristics graphs........................................................................................................................ 10
• Added the Clock Halt Auto-recover section.......................................................................................................................... 29
• Added the Sample Rate on the Fly Change section ............................................................................................................ 29
• Added the Thermal Foldback section ................................................................................................................................... 35
• Changed the Device State Control section .......................................................................................................................... 35
• Changed the DSP Memory Book, Page and BQ Coefficients Update section .................................................................... 41
• Added the Example Use section .......................................................................................................................................... 41
• Deleted 010:310K in Table 8 ................................................................................................................................................ 48
• Added the Inductor Selections section ................................................................................................................................. 76
• Added the Step 2: Speaker Tuning section.......................................................................................................................... 81
• Changed the Development Support section......................................................................................................................... 91
Changes from Original (May 2018) to Revision A
Page
• Released as Production Data................................................................................................................................................. 1
2 Submit Documentation Feedback
Product Folder Links: TAS5805M
Copyright © 2018, Texas Instruments Incorporated


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity TAS5805M SLASEH5C – MAY 2018 – REVISED DECEMBER 2018 TAS5805M 23-W , Inductor-Less, Digital Input, Stereo, Closed-Loop Class-D Audio Amplifier wi th Enhanced Processing and Low Power Di ssipation 1 Features •1 Supports Mul tiple Output Configurations – 2 × 23 W in 2.0 Mode (8-Ω, 21 V, THD+N=1%) 45 W in Mono Mode (4-Ω, 21 V, THD+N =1%) • Excellent Audio Performance THD+N ≤ 0.03% at 1 W, 1 kHz, PVDD = 12 V – SNR ≥ 107 dB (A-weighted), Noise Level < 40 µVRMS • Low Quiesce nt Current with Hybrid Modulation – 1 6.5 mA at PVDD = 13.5 V , 22 µH + 0.68 µF Filter • Flexible Power Supply C onfigurations – PVDD: 4.5 V to 26.4 V – DVDD and I/O: 1.8 V or 3.3 V • F lexible Audio I/O – I2S, LJ, RJ, TDM, 3-Wire Digital Audio Interface (No MCL K Required) – Supports 32, 44.1, 48, 88.2, 96 kHz Sample Rates – SDOUT for Audio Monitoring, Sub-Channel or Echo Cancellation • Enhanced Audio Processing – Multi-Band Advanced DRC a.
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