CY8C6246 MCU Datasheet

CY8C6246 Datasheet, PDF, Equivalent


Part Number

CY8C6246

Description

PSoC 62 MCU

Manufacture

Cypress Semiconductor

Total Page 30 Pages
Datasheet
Download CY8C6246 Datasheet


CY8C6246
PSoC 6 MCU: CY8C62x6,
CY8C62x7 Datasheet
PSoC 62 MCU
General Description
PSoC® 6 MCU is a high-performance, ultra-low-power and secure MCU platform, purpose-built for IoT applications. The PSoC 62
product family, based on the PSoC 6 MCU platform, is a combination of a high-performance microcontroller with low-power flash
technology, digital programmable logic, high-performance analog-to-digital and standard communication and timing peripherals.
Features
32-bit Dual CPU Subsystem
150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle
multiply (Floating Point and Memory Protection Unit)
100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply
and MPU
User-selectable core logic operation at either 1.1 V or 0.9 V
Active CPU current slope with 1.1-V core operation
Cortex-M4: 40 µA/MHz
Cortex-M0+: 20 µA/MHz
Active CPU current slope with 0.9-V core operation
Cortex-M4: 22 µA/MHz
Cortex-M0+: 15 µA/MHz
Two DMA controllers with 16 channels each
Memory Subsystem
1-MB application flash, 32-KB auxiliary flash (AUXflash), and
32-KB supervisory flash (Sflash); read-while-write (RWW)
support. Two 8-KB flash caches, one for each CPU.
288-KB SRAM with power and data retention control
One-time-programmable (OTP) 1-Kb eFuse array
Low-Power 1.7-V to 3.6-V Operation
Six power modes for fine-grained power management
Deep Sleep mode current of 7 µA with 64-KB SRAM retention
On-chip Single-In Multiple Out (SIMO) DC-DC Buck converter,
<1 µA quiescent current
Backup domain with 64 bytes of memory and Real-Time Clock
Flexible Clocking Options
On-chip crystal oscillators (4 to 35 MHz, and 32 kHz)
Phase-locked Loop (PLL) for multiplying clock frequencies
8 MHz Internal Main Oscillator (IMO) with ±2% accuracy
Ultra-low-power 32-kHz Internal Low-speed Oscillator (ILO)
Frequency Locked Loop (FLL) for multiplying IMO frequency
Quad SPI (QSPI)/Serial Memory Interface (SMIF)
Execute-In-Place (XIP) from external Quad SPI Flash
On-the-fly encryption and decryption
4-KB cache for greater XIP performance with lower power
Supports single, dual, quad, dual-quad, and octal interfaces w/
throughput up to 640 Mbps
Serial Communication
Nine run-time configurable serial communication blocks
(SCBs)
Eight SCBs: configurable as SPI, I2C, or UARTs
One Deep Sleep SCB: configurable as SPI or I2C
Audio Subsystem
Two PDM channels and one I2S channel with TDM mode
Timing and Pulse-Width Modulation
Thirty-two timer/counter pulse-width modulators (TCPWM)
Center-aligned, Edge, and Pseudo-random modes
Comparator-based triggering of Kill signals
Programmable Analog
12-bit 1-Msps SAR ADC with differential and single-ended
modes and 16-channel sequencer with result averaging
Two low-power comparators available in Deep Sleep and
Hibernate modes
Built-in temp sensor connected to ADC
One 12-bit voltage mode DAC with < 5-µs settling time
Two opamps with low-power operation modesUSB Full-Speed
Dual-role Host and Device interface
Up to 100 Programmable GPIOs
Two Smart I/O ports (16 I/Os) enable Boolean operations on
GPIO pins; available during Deep Sleep
Programmable drive modes, strengths, and slew rates
Six overvoltage-tolerant (OVT) pins
Capacitive Sensing
Cypress CapSense provides best-in-class SNR, liquid
tolerance, and proximity sensing
Enables dynamic usage of both self and mutual sensing
Automatic hardware tuning (SmartSense™)
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-18449 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 20, 2019

CY8C6246
PSoC 6 MCU: CY8C62x6,
CY8C62x7 Datasheet
Security Built into Platform Architecture
ROM-based root of trust via uninterruptible Secure Boot
Step-wise authentication of execution images
Secure execution of code in execute-only mode for protected
routines
All Debug and Test ingress paths can be disabled
Up to eight Protection Contexts
Cryptography Accelerators
Hardware acceleration for symmetric and asymmetric
cryptographic methods and hash functions
True Random Number Generator (TRNG) function
Programmable Digital
12 programmable logic blocks, each with 8 Macrocells and an
8-bit data path (called universal digital blocks or UDBs)
Usable as drag-and-drop Boolean primitives (gates, registers),
or as Verilog programmable blocks
Cypress-provided peripheral component library using UDBs to
implement functions such as Communication peripherals (for
example, LIN, UART, SPI, I2C, S/PDIF and other protocols),
Waveform Generators, Pseudo-Random Sequence (PRS)
generation, and many other functions.)
Profiler
Eight counters provide event or duration monitoring of on-chip
resources
Packages
124-BGA package
80-WLCSP (in 0.33 and 0.43 mm heights)
Thin 80-WLCSP package (0.33 mm height) (qualification in
process)
Document Number: 002-18449 Rev. *H
Page 2 of 76


Features PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet PSoC 62 MCU General Description PSoC 6 MCU is a high-performance, ultra-lo w-power and secure MCU platform, purpos e-built for IoT applications. The PSoC 62 product family, based on the PSoC 6 MCU platform, is a combination of a hig h-performance microcontroller with low- power flash technology, digital program mable logic, high-performance analog-to -digital and standard communication and timing peripherals. Features 32-bit Dual CPU Subsystem ■ 150-MHz Arm® Co rtex®-M4F (CM4) CPU with single-cycle multiply (Floating Point and Memory Pro tection Unit) ■ 100-MHz Cortex-M0+ (C M0+) CPU with single-cycle multiply and MPU ■ User-selectable core logic ope ration at either 1.1 V or 0.9 V ■ Act ive CPU current slope with 1.1-V core o peration ❐ Cortex-M4: 40 µA/MHz ❐ Cortex-M0+: 20 µA/MHz ■ Active CPU c urrent slope with 0.9-V core operation ❐ Cortex-M4: 22 µA/MHz ❐ Cortex-M0 +: 15 µA/MHz ■ Two DMA controllers with 16 channels each Memory Subsystem ■ 1-MB applic.
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