BD71850MWV Management Datasheet

BD71850MWV Datasheet, PDF, Equivalent


Part Number

BD71850MWV

Description

Programmable Power Management

Manufacture

ROHM

Total Page 30 Pages
Datasheet
Download BD71850MWV Datasheet


BD71850MWV
Datasheet
Power Management Integrated Circuit
BD71850MWV
General Description
BD71850MWV is a programmable Power Management
IC (PMIC) for powering single-core, dual-core, and
quad-core SoCs such as NXP-i.MX 8M Nano. It is
optimized for low BOM cost and compact solution
footprint. It integrates 6 Buck regulators and 6 LDOs to
provide all the power rails required by the SoC and the
commonly used peripherals.
QFN package and pinout support low cost Type 3
(non-HDI) PCB. Programmable power sequencing
and output voltages, flexible power state control for
easier system design and supports a wide variety of
processors and system implementations.
Features
6 Buck Regulators
2.0 MHz Switching Frequency.
(BUCK1, BUCK2, BUCK5, BUCK7, and BUCK8).
1.5MHz Switching Frequency. (BUCK6)
Target Efficiency: 83% to 95%.
Output Current & Voltage.
BUCK1: 3.0 A, 0.7 V to 1.3 V/10 mV step, DVS
BUCK2: 3.0 A, 0.7 V to 1.3 V/10 mV step, DVS
BUCK5: 3.0 A, 0.70 V to 1.35 V/8steps, DVS
BUCK6: 3.0 A, 2.6 V to 3.3 V/100 mV step
BUCK7: 1.5 A, 1.605 V to 1.995 V/8steps
BUCK8: 3.0 A, 0.8 V to 1.4 V/10 mV step
6ch Linear Regulators (6 LDOs)
LDO1: 10 mA, 3.0 V to 3.3 V, 1.6 V to 1.9 V
LDO2: 10 mA, 0.9 V, 0.8 V
LDO3: 300 mA, 1.8 V to 3.3 V
LDO4: 250 mA, 0.9 V to 1.8 V
LDO5: 300 mA, 0.8 V to 3.3 V
LDO6: 300 mA, 0.9 V to 1.8 V
Power Mux Switch
1.8V Input: 500 mΩ(Max)
3.3V Input: 500 mΩ(Max)
32.768 kHz Crystal Oscillator Driver
Power Button Detector
Protection and Monitoring: Soft Start, Power Rails Fault
Detection, UVLO, OVP and TSD
OTP Configurable Power Sequencing
OTP and Software Programmable Output Voltage,
Ramp rates.
Hardware Signaling with SoC for Transition into or out
of Low Power States
Interfaces:
I2C: 100 kHz/400 kHz, 1 MHz
Power-on Reset Output: POR_B, RTC_RESET_B,
Watchdog Reset Input: WDOG_B:
Power State Control:
PMIC_STBY_REQ, PMIC_ON_REQ, PWRON_B
Interrupt to SoC: IRQ_B
Type3 PCB Applicable
Key Specifications
Input Voltage Range (VSYS):
SNVS State Current:
SUSPEND State Current:
IDLE State Current:
RUN State Current:
Operating Temperature Range:
2.7 V to 5.5 V
30 μA(Typ)
115 μA(Typ)
125 μA(Typ)
125 μA(Typ)
-40°C to +85°C
Applications
Streaming Media Boxes and Dongles
AV Receivers and Wireless Sound Bars
Industrial HMI, SBC, IPC and Panel Computer
Package
UQFN56BV7070
W(Typ) x D(Typ) x H(Max)
7.00 mm x 7.00 mm x 1.00 mm
Product structure : Silicon integrated circuit. This product has no designed protection against radioactive rays
www.rohm.com
© 2019 ROHM Co., Ltd. All rights reserved.
TSZ2211114001
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TSZ02201-0Q2Q0A500680-1-2
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BD71850MWV
BD71850MWV
Contents
General Description ................................................................................................................................................................1
Features .................................................................................................................................................................................1
Key Specifications...................................................................................................................................................................1
Applications ............................................................................................................................................................................1
Package
W(Typ) x D(Typ) x H(Max) ...........................................................................................................1
1. Introduction.....................................................................................................................................................................7
1.1. Terminology ............................................................................................................................................................7
1.2. System Power Map & Typical Application Circuit ......................................................................................................8
1.3. Pin Configuration .................................................................................................................................................. 10
1.4. Pin Description...................................................................................................................................................... 11
1.5. I/O Equivalence Circuit .......................................................................................................................................... 12
1.6. Power Rail ............................................................................................................................................................ 13
1.7. Register Map ........................................................................................................................................................ 14
1.8. ESD...................................................................................................................................................................... 16
2. Operating Conditions .................................................................................................................................................... 17
2.1. Absolute Maximum Ratings (Ta=25 ˚C).................................................................................................................. 17
2.2. Thermal Resistance .............................................................................................................................................. 17
2.3. Recommended Operating Conditions .................................................................................................................... 18
2.4. Current Consumption ............................................................................................................................................ 18
2.5. Power Reference and Detectors (UVLO)................................................................................................................ 19
3. Power State Control ...................................................................................................................................................... 20
3.1. Power Control Signals........................................................................................................................................... 20
3.1.1. PWRON_B ................................................................................................................................................... 21
3.1.2. PMIC_ON_REQ............................................................................................................................................ 21
3.1.3. PMIC_STBY_REQ........................................................................................................................................ 21
3.1.4. WDOG_B ..................................................................................................................................................... 21
3.1.5. RTC_RESET_B ............................................................................................................................................ 22
3.1.6. POR_B......................................................................................................................................................... 22
3.2. Power States ........................................................................................................................................................ 23
3.2.1. Power State Diagram .................................................................................................................................... 23
3.2.2. Power State Register .................................................................................................................................... 24
3.2.3. Power State Definition................................................................................................................................... 26
3.2.4. Power State Control Events........................................................................................................................... 27
3.2.4.1.
Reset Event .......................................................................................................................................... 27
3.2.4.2.
Emergency Shutdown Event.................................................................................................................. 29
3.2.5. Power State Transitions................................................................................................................................. 29
3.2.5.1.
OFF to READY ..................................................................................................................................... 29
3.2.5.2.
READY to SNVS................................................................................................................................... 30
3.2.5.3.
SNVS to RUN ....................................................................................................................................... 33
3.2.5.4.
RUN to IDLE......................................................................................................................................... 35
3.2.5.5.
IDLE to RUN......................................................................................................................................... 35
3.2.5.6.
RUN to SUSPEND ................................................................................................................................ 35
3.2.5.7.
SUSPEND to RUN ................................................................................................................................ 35
3.2.5.8.
IDLE to SUSPEND................................................................................................................................ 36
3.2.5.9.
Emergency Shutdown ........................................................................................................................... 36
3.2.5.10. VR Fault ............................................................................................................................................... 37
3.2.5.11. EMG to OFF ......................................................................................................................................... 41
3.2.5.12. EMG to READY .................................................................................................................................... 42
3.2.5.13. EMG_STAY Condition ........................................................................................................................... 43
3.2.5.14. Warm Reset.......................................................................................................................................... 43
3.2.5.15. PWROFF.............................................................................................................................................. 44
3.2.5.16. PWROFF to READY ............................................................................................................................. 46
3.2.5.17. PWROFF to SNVS................................................................................................................................ 46
3.2.5.18. PWRON_B Functionality ....................................................................................................................... 46
3.3. Power Sequence................................................................................................................................................... 48
3.3.1. Power ON Sequence..................................................................................................................................... 48
3.3.2. Power OFF Sequence................................................................................................................................... 50
3.3.3. RUN to IDLE................................................................................................................................................. 54
3.3.4. IDLE to RUN................................................................................................................................................. 55
3.3.5. RUN to SUSPEND........................................................................................................................................ 56
3.3.6. SUSPEND to RUN........................................................................................................................................ 57
3.3.7. IDLE to SUSPEND........................................................................................................................................ 58
3.3.8. Emergency Shutdown ................................................................................................................................... 59
3.3.9. Warm Reset.................................................................................................................................................. 60
3.3.10. Reset Source Indicators ................................................................................................................................ 61
4. I2C and Interrupt ........................................................................................................................................................... 62
4.1. I2C Bus Interface .................................................................................................................................................. 62
4.1.1. I2C Bus Interface Overview ........................................................................................................................... 62
4.1.2. I2C Bus Interface Electrical Characteristics .................................................................................................... 63
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© 2019 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
2/116
TSZ02201-0Q2Q0A500680-1-2
27.Sep.2019 Rev.001


Features Datasheet Power Management Integrated C ircuit BD71850MWV General Description  BD71850MWV is a programmable Power Management IC (PMIC) for powering sing le-core, dual-core, and quad-core SoC s such as NXP-i.MX 8M Nano. It is opti mized for low BOM cost and compact solu tion footprint. It integrates 6 Buck re gulators and 6 LDO’s to provide all t he power rails required by the SoC and the commonly used peripherals.  QFN package and pinout support low cost Typ e 3 (non-HDI) PCB. Programmable power s equencing and output voltages, flexible power state control for easier system design and supports a wide variety of p rocessors and system implementations. F eatures  6 Buck Regulators  2.0 M Hz Switching Frequency. (BUCK1, BUCK2, BUCK5, BUCK7, and BUCK8).  1.5MHz Sw itching Frequency. (BUCK6)  Target E fficiency: 83% to 95%.  Output Curre nt & Voltage. BUCK1: 3.0 A, 0.7 V to 1. 3 V/10 mV step, DVS BUCK2: 3.0 A, 0.7 V to 1.3 V/10 mV step, DVS BUCK5: 3.0 A, 0.70 V to 1.35 V/8steps, DVS BUCK6: 3.0 A.
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