Step-Down Converter. TPS54320 Datasheet

TPS54320 Converter. Datasheet pdf. Equivalent

TPS54320 Datasheet
Recommendation TPS54320 Datasheet
Part TPS54320
Description 3-A Synchronous Step-Down Converter
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Texas Instruments TPS54320
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
Reference
Design
TPS54320
SLVS982C – AUGUST 2010 – REVISED APRIL 2018
TPS54320 4.5- to 17-V Input, 3-A Synchronous Step Down SWIFT™ Converter
1 Features
1 Integrated 57-m/ 50-mMOSFETs
• Split Power Rail: 1.6 to 17 V on PVIN
• 200-kHz to 1.2-MHz Switching Frequency
• Synchronizes to External Clock
• 0.8-V Voltage Reference With ±1% Accuracy
• Low 2-µA Shutdown Quiescent Current
• Hiccup Overcurrent Protection
• Monotonic Start-Up into Prebiased Outputs
• –40°C to 150°C Operating Junction Temperature
Range
• Pin-to-Pin Compatible With the TPS54620
• Adjustable Slow Start/Power Sequencing
• Power Good Output for Undervoltage and
Overvoltage Monitoring
• Adjustable Input Undervoltage Lockout (UVLO)
• Supported by SwitcherPro™ Software Tool
• For SWIFT™ Documentation and SwitcherPro,
Visit www.ti.com/swift
• Create a Custom Design Using the TPS54320
With the WEBENCH® Power Designer
2 Applications
• Broadband, Networking, and Communication
Infrastructure
• Automated Test and Medical Equipment
• DSP and FPGA Point-of-Load Applications from
12-V Bus
Simplified Schematic
VIN
Cin
Css Rrt C2
PVIN
VIN
TPS54320
BOOT
Cboot
EN PH
PWRGD
Lo
Co
SS/TR VSENSE
RT/CLK
COMP GND
R3 Exposed
Thermal
C1 Pad
VOUT
R1
R2
3 Description
The TPS54320 is a full-featured 17-V, 3-A
synchronous step-down converter which is optimized
for small designs through high efficiency and
integrated high-side and low-side MOSFETs. Further
space savings are achieved through current mode
control, which reduces component count, and by
selecting a high switching frequency, reducing
footprint of the inductor.
The output voltage start-up ramp is controlled by the
SS/TR pin which allows operation as either a stand-
alone power supply or in tracking situations. Power
sequencing is also possible by correctly configuring
the enable and the open drain power good pins.
Cycle by cycle current limiting on the high-side FET
protects the device in overload situations and is
enhanced by a low-side sourcing current limit which
prevents current runaway. Hiccup protection is
triggered if the overcurrent condition has persisted for
longer than the preset time. Thermal shutdown
disables the part when die temperature exceeds
thermal shutdown temperature. The TPS54320 is
available in a 14-pin, 3.5-mm × 3.5-mm VQFN,
thermally enhanced package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS54320
VQFN (14)
3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
100
95
90
85
80
75
70
65
60
55
50
0
Efficiency vs Load Current
VOUT = 1.8 V VOUT = 3.3 V VOUT = 5 V
VIN = 12 V,
Fsw = 500 kHz
0.5 1 1.5 2 2.5 3
Load Current - A
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



Texas Instruments TPS54320
TPS54320
SLVS982C – AUGUST 2010 – REVISED APRIL 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics .............................................. 7
7 Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 21
8 Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application ................................................. 23
9 Power Supply Recommendations...................... 33
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Layout Example .................................................... 34
11 Device and Documentation Support ................. 35
11.1 Device Support...................................................... 35
11.2 Documentation Support ........................................ 35
11.3 Trademarks ........................................................... 35
11.4 Electrostatic Discharge Caution ............................ 35
11.5 Glossary ................................................................ 35
12 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2014) to Revision C
Page
• Added links for WEBENCH and top navigator icon for TI reference design ......................................................................... 1
• Changed "Handling Ratings" to "ESD Ratings"; move Storage temperature to "Abs Max" table ......................................... 4
• Changed RθJA from "47.2" to "42.8" °C/W; RθJC(top)from "64.8" to "39.4" °C/W; RθJB from "14.4" to "15.9" °C/W; ψJT
from "0.5" to "0.9"°C/W ; ψJB from "14.7" to "15.9"°C/W ; RθJC(bot) from "3.2" to "3.9" °C/W................................................... 5
• Changed "Ih = 3.4 μA" to "Ih = 2.25 μA" in Equation 3.......................................................................................................... 14
• Changed "OVP threshold" to "VSENSE falling (Good) threshold of 106%" in last sentence of Output Overvoltage
Protection (OVP) ................................................................................................................................................................. 17
• Corrected pin name from SYNC to RT/CLK in Synchronization (CLK Mode) ..................................................................... 22
Changes from Revision A (September 2010) to Revision B
Page
• Added Handling Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
• Removed Bill of Materials .................................................................................................................................................... 32
Changes from Original (August 2010) to Revision A
Page
• Changed Applications itemized list......................................................................................................................................... 1
• Changed Figure 34 - Typical App Circuit ............................................................................................................................. 23
• Changed Figure 47 image with new plot .............................................................................................................................. 30
• Changed Figure 51 image with new plot .............................................................................................................................. 30
• Changed Figure 55 Thermal Signature image ..................................................................................................................... 31
• Added C6 to Bill of Material and changed C8 RefDes to C9 with size 1210 to match SLVU380 User's Guide BoM.......... 32
2 Submit Documentation Feedback
Product Folder Links: TPS54320
Copyright © 2010–2018, Texas Instruments Incorporated



Texas Instruments TPS54320
www.ti.com
5 Pin Configuration and Functions
RHL Package
14-Pin VQFN
Top View
RT/CLK
1
PWRGD
14
TPS54320
SLVS982C – AUGUST 2010 – REVISED APRIL 2018
GND 2
GND 3
PVIN 4
PVIN 5
VIN 6
Exposed
Thermal Pad
(15)
13 BOOT
12 PH
11 PH
10 EN
9 SS/TR
7
VSENSE
8
COMP
PIN
NAME
RT/CLK
GND
PVIN
VIN
VSENSE
COMP
SS/TR
EN
PH
BOOT
PWRGD
Exposed
thermal PAD
Pin Functions
DESCRIPTION
NO.
1
Automatically selects between RT mode and CLK mode. An external timing resistor adjusts the switching
frequency of the device; In CLK mode, the device synchronizes to an external clock.
2
Return for control circuitry and low-side power MOSFET.
3
4
Power input. Supplies the power switches of the power converter.
5
6 Supplies the control circuitry of the power converter.
7 Inverting input of the gm error amplifier.
8
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation to this
pin.
9
Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time.
The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing.
10 Enable pin. Float to enable. Adjust the input undervoltage lockout with two resistors.
11
The switch node
12
13
A bootstrap cap is required between BOOT and PH. The voltage on this cap carries the gate drive voltage for the
high-side MOSFET.
14
Open-drain Power Good fault pin. Asserts low due to thermal shutdown, undervoltage, overvoltage, EN shutdown,
or during slow start.
15 Thermal pad of the package and signal ground. It must be soldered down for proper operation.
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS54320
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