Step-Down Switcher. TPS54325 Datasheet

TPS54325 Switcher. Datasheet pdf. Equivalent

TPS54325 Datasheet
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Part TPS54325
Description 3-A Output Synchronous Step-Down Switcher
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TPS54325
SLVS932F – MAY 2009 – REVISED NOVEMBER 2014
TPS54325 4.5-V to 18-V, 3-A Output Synchronous Step Down
Switcher with Integrated FET
1 Features
1 D-CAP2™ Mode Enables Fast Transient
Response
• Low Output Ripple and Allows Ceramic Output
Capacitor
• Wide VCC Input Voltage Range: 4.5 V to 18 V
• Wide VIN Input Voltage Range: 2.0 V to 18 V
• Output Voltage Range: 0.76 V to 5.5 V
• Highly Efficient Integrated FET’s Optimized for
Lower Duty Cycle Applications – 120 m(High
Side) and 70 m(Low Side)
• High Efficiency, less than 10 μA at shutdown
• High Initial Bandgap Reference Accuracy
• Adjustable Soft Start
• Pre-Biased Soft Start
• 700-kHz Switching Frequency (fSW)
• Cycle By Cycle Over Current Limit
• Power Good Output
2 Applications
• Wide Range of Applications for Low Voltage
System
– Digital TV Power Supply
– High Definition Blu-ray Disc™ Players
– Networking Home Terminal
– Digital Set Top Box (STB)
3 Description
The TPS54325 device is an adaptive on-time D-
CAP2™ mode synchronous buck converter. The
TPS54325 device enables system designers to
complete the suite of various end equipment’s power
bus regulators with a cost effective, low component
count, low standby current solution.
The main control loop for the TPS54325 uses the D-
CAP2™ mode control which provides a very fast
transient response with no external components. The
TPS54325 also has a proprietary circuit that enables
the device to adapt to both low equivalent series
resistance (ESR) output capacitors, such as
POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors. The device operates from 4.5-V to 18-V
VCC input , and from 2.0-V to 18-V VIN input power
supply voltage. The output voltage can be
programmed between 0.76 V and 5.5 V. The device
also features an adjustable slow start time and a
power good function. The TPS54325 is available in
the 14 pin HTSSOP package, and designed to
operate from –40°C to 85°C.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS54325
HTSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
TPS54325
Load Transient Response
VOUT (50 mV / div)
100 µs / div
IOUT (2 A / div)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



Texas Instruments TPS54325
TPS54325
SLVS932F – MAY 2009 – REVISED NOVEMBER 2014
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Simplified Schematic............................................. 1
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 Handling Ratings....................................................... 4
7.3 Thermal Information .................................................. 4
7.4 Recommended Operating Conditions....................... 5
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics .............................................. 7
8 Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9 Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
11.3 Thermal Considerations ........................................ 17
12 Device and Documentation Support ................. 18
12.1 Device Support...................................................... 18
12.2 Documentation Support ........................................ 18
12.3 Trademarks ........................................................... 18
12.4 Electrostatic Discharge Caution ............................ 18
12.5 Glossary ................................................................ 18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (January 2014) to Revision F
Page
• Added, updated, or renamed the following sections: Device Information Table, Application and Implementation;
Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and
Ordering Information .............................................................................................................................................................. 1
Changes from Revision D (January 2012) to Revision E
Page
• Changed text in the Bootstrap Capacitor Selection from "between the VREG5 to GND pin for proper operation" to
"between the VBST to SW pin for proper operation............................................................................................................. 13
Changes from Revision C (July 2011) to Revision D
Page
• Removed (SWIFT™) from the data sheet title ....................................................................................................................... 1
• Added conditions to Typical Characteristics........................................................................................................................... 7
Changes from Revision B (March 2011) to Revision C
Page
• Changed EN high-level input voltage from min of 2.0 V to min of 1.6 V................................................................................ 5
• Changed EN low-level input voltage from max of 0.48 V to max of 0.4 V ............................................................................. 5
Changes from Original (May 2009) to Revision A
Page
• Changed TA, for the current limit, Iocl, From: 25°C to –40°C To: 85°C and 3.5 A was added at the MIN value .................... 6
2 Submit Documentation Feedback
Product Folder Links: TPS54325
Copyright © 2009–2014, Texas Instruments Incorporated



Texas Instruments TPS54325
www.ti.com
6 Pin Configuration and Functions
14-Pin
PWP PACKAGE
Top View
VO 1
VFB 2
VREG5 3
SS 4
GND 5
POWERPAD
TPS54325
PWP
HTSSOP14
TPS54325
SLVS932F – MAY 2009 – REVISED NOVEMBER 2014
14 VCC
13 VIN
12 VBST
11 SW2
10 SW1
PG 6
9 PGND2
EN 7
8 PGND1
NAME
VO
VFB
VREG5
SS
GND
PG
EN
PGND1,
PGND2
PIN
NO.
1
2
3
4
5
6
7
8, 9
SW1, SW2
10, 11
VBST
VIN
VCC
PowerPAD™
12
13
14
––
Pin Functions
I/O DESCRIPTION
I Connect to output of converter. This terminal is used for On-Time Adjustment.
I Converter feedback input. Connect with feedback resistor divider.
O 5.5 V power supply output. A capacitor (typical 1μF) should be connected to GND.
I Soft-start control. A external capacitor should be connected to GND.
–– Signal ground pin
O Open drain power good output
I Enable control input
––
Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND and
GND strongly together near the IC.
O
Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current
comparators.
O
Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to
respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin.
I Power input and connected to high side NFET drain
I Supply input for 5 V internal linear regulator for the control circuitry
––
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected
to PGND.
Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: TPS54325
Submit Documentation Feedback
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