Fanout Buffer. 8302 Datasheet

8302 Buffer. Datasheet pdf. Equivalent

8302 Datasheet
Recommendation 8302 Datasheet
Part 8302
Description LVCMOS / LVTTL Fanout Buffer
Feature 8302; Low Skew, 1-to-2 LVCMOS / LVTTL Fanout Buffer 8302 Data Sheet GENERAL DESCRIPTION The 8302 is a lo.
Manufacture Renesas
Datasheet
Download 8302 Datasheet




Renesas 8302
Low Skew, 1-to-2
LVCMOS / LVTTL Fanout Buffer
8302
Data Sheet
GENERAL DESCRIPTION
The 8302 is a low skew, 1-to-2 LVCMOS/LVTTL Fanout
Buffer. The 8302 hasa single ended clock input. The
single endedclock input accepts LVCMOS or LVTTL
input levels. The 8302 features a pair of LVCMOS/
LVTTL outputs. The 8302 is characterized at full 3.3V for
input VDD,and mixed 3.3V and 2.5V for output operating
supply modes (VDDO). Guaranteed output and part-to-part
skew characteristics make the 8302 ideal for clock distribution
applications demanding well defined performance and
repeatibility.
FEATURES
• 2 LVCMOS / LVTTL outputs
• LVCMOS / LVTTL clock input accepts LVCMOS
or LVTTL input levels
• Maximum output frequency: 200MHz
• Output skew: 25ps (typical)
• Part-to-part skew: 250ps (typical)
• Small 8 lead SOIC package saves board space
• Full 3.3V or 3.3V core, 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
CLK
Q0
Q1
©2016 Integrated Device Technology, Inc
PIN ASSIGNMENT
VDDO
VDD
CLK
GND
1
2
3
4
8 Q0
7 GND
6 VDDO
5 Q1
8302
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
1 Revision D March 4, 2016



Renesas 8302
8302 Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 6
VDDO
Power
Output supply pins.
2 VDD Power
Core supply pin.
3 CLK Input Pulldown LVCMOS / LVTTL clock input.
4,7
GND
Power
Power supply ground.
5 Q1 Output
Single clock output. LVCMOS / LVTTL interface levels.
8 Q0 Output
Single clock output. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
CPD
RPULLDOWN
ROUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pulldown Resistor
Output Impedance
Test Conditions
VDD, VDDO = 3.465V
VDD = 3.465V, VDDO = 2.625V
Minimum
5
Typical
4
22
16
51
7
Maximum
12
Units
pF
pF
pF
kΩ
Ω
©2016 Integrated Device Technology, Inc
2
Revision D March 4, 2016



Renesas 8302
8302 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA 112.7°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VDD
VDDO
IDD
IDDO
Parameter
Core Supply Voltage
Output Power Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
13
4
Units
V
V
mA
mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VIH
VIL
I
IH
IIL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK
CLK
VOH Output High Voltage
VOL Output Low Voltage
Test Conditions
V = V = 3.465V
DD IN
VDD = 3.465V, VIN = 0V
50Ω to VDDO/2
IOH = -100µA
50Ω to VDDO/2
IOL = 100µA
Minimum
2
-0.3
Typical
-5
2.6
2.9
Maximum
VDD + 0.3
0.8
150
0.5
0.2
Units
V
V
µA
µA
V
V
V
V
TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
tsk(o)
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
ƒ 200MHz
200 MHz
1.9 2.35 2.8 ns
25 85 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4
250 800 ps
tR Output Rise Time
tF Output Fall Time
odc Output Duty Cycle
20% to 80%
20% to 80%
ƒ 133MHz
133MHz < ƒ 200MHz
300
300
45
40
800 ps
800 ps
55 %
60 %
Parameters measured at fMAX unless otherwise noted.
NOTE 1: Measured from V /2 of the input to V /2 of the output.
DD DDO
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
3
Revision D March 4, 2016





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