8302 Buffer Datasheet

8302 Datasheet, PDF, Equivalent


Part Number

8302

Description

LVCMOS / LVTTL Fanout Buffer

Manufacture

Renesas

Total Page 11 Pages
Datasheet
Download 8302 Datasheet


8302
Low Skew, 1-to-2
LVCMOS / LVTTL Fanout Buffer
8302
Data Sheet
GENERAL DESCRIPTION
The 8302 is a low skew, 1-to-2 LVCMOS/LVTTL Fanout
Buffer. The 8302 hasa single ended clock input. The
single endedclock input accepts LVCMOS or LVTTL
input levels. The 8302 features a pair of LVCMOS/
LVTTL outputs. The 8302 is characterized at full 3.3V for
input VDD,and mixed 3.3V and 2.5V for output operating
supply modes (VDDO). Guaranteed output and part-to-part
skew characteristics make the 8302 ideal for clock distribution
applications demanding well defined performance and
repeatibility.
FEATURES
• 2 LVCMOS / LVTTL outputs
• LVCMOS / LVTTL clock input accepts LVCMOS
or LVTTL input levels
• Maximum output frequency: 200MHz
• Output skew: 25ps (typical)
• Part-to-part skew: 250ps (typical)
• Small 8 lead SOIC package saves board space
• Full 3.3V or 3.3V core, 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
CLK
Q0
Q1
©2016 Integrated Device Technology, Inc
PIN ASSIGNMENT
VDDO
VDD
CLK
GND
1
2
3
4
8 Q0
7 GND
6 VDDO
5 Q1
8302
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
1 Revision D March 4, 2016

8302
8302 Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 6
VDDO
Power
Output supply pins.
2 VDD Power
Core supply pin.
3 CLK Input Pulldown LVCMOS / LVTTL clock input.
4,7
GND
Power
Power supply ground.
5 Q1 Output
Single clock output. LVCMOS / LVTTL interface levels.
8 Q0 Output
Single clock output. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
CPD
RPULLDOWN
ROUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pulldown Resistor
Output Impedance
Test Conditions
VDD, VDDO = 3.465V
VDD = 3.465V, VDDO = 2.625V
Minimum
5
Typical
4
22
16
51
7
Maximum
12
Units
pF
pF
pF
kΩ
Ω
©2016 Integrated Device Technology, Inc
2
Revision D March 4, 2016


Features Low Skew, 1-to-2 LVCMOS / LVTTL Fanout B uffer 8302 Data Sheet GENERAL DESCRIP TION The 8302 is a low skew, 1-to-2 LVC MOS/LVTTL Fanout Buffer. The 8302 hasa single ended clock input. The single en dedclock input accepts LVCMOS or LVTTL input levels. The 8302 features a pair of LVCMOS/ LVTTL outputs. The 8302 is c haracterized at full 3.3V for input VDD ,and mixed 3.3V and 2.5V for output ope rating supply modes (VDDO). Guaranteed output and part-to-part skew characteri stics make the 8302 ideal for clock dis tribution applications demanding well d efined performance and repeatibility. FEATURES • 2 LVCMOS / LVTTL outputs LVCMOS / LVTTL clock input accepts L VCMOS or LVTTL input levels • Maximum output frequency: 200MHz • Output sk ew: 25ps (typical) • Part-to-part ske w: 250ps (typical) • Small 8 lead SOI C package saves board space • Full 3. 3V or 3.3V core, 2.5V supply modes • 0°C to 70°C ambient operating tempera ture • Lead-Free package fully RoHS compliant BLOCK DIAGRAM CLK Q0 Q1 ©2016 In.
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