4953 Transistor Datasheet

4953 Datasheet, PDF, Equivalent


Part Number

4953

Description

Dual P-Channel Enhancement Mode Field Effect Transistor

Manufacture

CXW

Total Page 6 Pages
Datasheet
Download 4953 Datasheet


4953
Dual P - Channel Enhancement Mode Field Effect Transistor 4953
4953 DATASHEET
P R ODUC T S UMMAR Y
VDS S
-30V
ID
-5.3A
R DS (ON) ( m ) Typ
50 @ VG S = -10V
70 @ VG S = -4.5V
F E AT UR E S
S uper high dense cell design for low R DS(ON).
R ugged and reliable.
S urface Mount P ackage.
D1 D2
4953
SIYWW
G1 G2
S1 S2
SOP-8 top view
Marking and pin assignment
Schematic diagram
ABS OLUTE MAXIMUM R ATINGS (TA=25 C unless otherwise noted)
P arameter
Drain-S ource Voltage
Gate-S ource Voltage
Drain C urrent-C ontinuous a @ TJ=25 C
-P ulsed b
Drain-S ource Diode Forward C urrent a
Maximum P ower Dissipation a
Operating Junction and S torage
Temperature R ange
S ymbol
VDS
VGS
ID
IDM
IS
PD
TJ, TSTG
Limit
-30
20
-5.3
-35
1.7
2
-55 to 150
Unit
V
V
A
A
A
W
C
THE R MAL CHAR ACTE R IS TICS
Thermal R esistance, Junction-to-Ambient a
R JA
62.5
C /W
1
www.cxwic.com

4953
Dual P - Channel Enhancement Mode Field Effect Transistor 4953
4953 DATASHEET
E LE CTR ICAL CHAR ACTE R IS TICS (TA=25 C unless otherwise noted)
P a ra meter
S ymbol
C ondition
Min Typ C Max Unit
OFF CHARACTERISTICS
Drain-S ource Breakdown Voltage BVDSS VGS =0V, ID =-250uA -30
Zero Gate Voltage Drain Current IDSS VDS =-24V, VGS =0V
Gate-Body Leakage
ON CHARACTERISTICS b
IGSS VGS = 20V, VDS= 0V
V
-1 uA
100 nA
Gate Threshold Voltage
V G S (th)
Drain-S ource On-S tate R esistance R DS(ON)
On-S tate Drain Current
Forward Transconductance
DYNAMIC CHARACTERISTICS c
ID(ON)
gFS
Input Capacitance
C IS S
Output Capacitance
COSS
R everse Transfer Capacitance
CRSS
SWITCHING CHARACTERISTICS c
Turn-On Delay Time
tD(ON)
R ise Time
tr
Turn-Off Delay Time
tD(O F F )
Fall Time
tf
VDS =VGS, ID = -250uA
VGS =-10V, ID = -4.6A
VGS =-4.5V, ID = -3.6A
VDS = -5V, VGS = -10V
VDS =-15V, ID = - 4.6A
-1 -1.5
50
70
-20
8
2V
65 m-ohm
85 m-ohm
A
S
VDS =-15V, VGS = 0V
f =1.0MHZ
525 PF
135 PF
70 PF
VD = -15V,
R L =15 ohm
ID = -1A,
VGEN = -10V,
R GEN =6 ohm
7 14 ns
13 24 ns
14 25 ns
9 17 ns
Total Gate Charge
Gate-S ource Charge
Gate-Drain Charge
Qg VDS=-15V,ID =-4.6A,VGS=-10V
VDS=-15V,ID =-4.6A,VGS=-4.5V
Qgs VDS =-15V, ID = -4.6A,
Qgd VGS =-10V
6 9 nC
8.1 nC
2.2 nC
2.0 nC
2 www.cxwic.com


Features Dual P - Channel Enhancement Mode Field Effect Transistor 4953 4953 DATASHEET P R ODUC T S UMMAR Y VDS S -30V ID -5 .3A R DS (ON) ( m Ω ) Typ 50 @ VG S = -10V 70 @ VG S = -4.5V F E AT UR E S S uper high dense cell design for low R DS(ON). R ugged and reliable. S urfac e Mount P ackage. D1 D2 4953 SIYWW G 1 G2 S1 S2 SOP-8 top view Marking and pin assignment Schematic diagram ABS OLUTE MAXIMUM R ATINGS (TA=25 C unless otherwise noted) P arameter Drain-S o urce Voltage Gate-S ource Voltage Drain C urrent-C ontinuous a @ TJ=25 C -P ul sed b Drain-S ource Diode Forward C urr ent a Maximum P ower Dissipation a Oper ating Junction and S torage Temperature R ange S ymbol VDS VGS ID IDM IS PD T J, TSTG Limit -30 20 -5.3 -35 1.7 2 -5 5 to 150 Unit V V A A A W C THE R MAL CHAR ACTE R IS TICS Thermal R esistan ce, Junction-to-Ambient a R JA 62.5 C /W 1 www.cxwic.com Dual P - Channel Enhancement Mode Field Effect Transist or 4953 4953 DATASHEET E LE CTR ICAL CHAR ACTE R IS TICS (TA=25.
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