DRA755 Processor Datasheet

DRA755 Datasheet, PDF, Equivalent


Part Number

DRA755

Description

Infotainment Applications Processor

Manufacture

etcTI

Total Page 30 Pages
Datasheet
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DRA755
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DRA756, DRA755, DRA754, DRA752
DRA751, DRA750, DRA746, DRA745, DRA744
SPRS950F – DECEMBER 2015 – REVISED MAY 2019
DRA75x, DRA74x Infotainment Applications Processor
Silicon Revision 2.0
1 Device Overview
1.1 Features
1
• Architecture designed for infotainment applications
• Video, image, and graphics processing support
– Full-HD video (1920 × 1080p, 60 fps)
– Multiple video input and video output
– 2D and 3D graphics
• Dual Arm® Cortex®-A15 microprocessor subsystem
• Up to two C66x floating-point VLIW DSP
– Fully object-code compatible with C67x and
C64x+
– Up to thirty-two 16 x 16-Bit fixed-point multiplies
per cycle
• Up to 2.5MB of on-chip L3 RAM
• Level 3 (L3) and level 4 (L4) interconnects
• Two DDR2/DDR3/DDR3L memory interface
(EMIF) modules
– Supports up to DDR2-800 and DDR3-1066
– Up to 2GB supported per EMIF
• Dual Arm® Cortex®-M4 Image Processing Units
(IPU)
• Up to two Embedded Vision Engines (EVEs)
• IVA subsystem
• Display subsystem
– Display controller with DMA engine and up to
three pipelines
– HDMI™ encoder: HDMI 1.4a and DVI 1.0
compliant
• Video Processing Engine (VPE)
• 2D-graphics accelerator (BB2D) subsystem
– Vivante® GC320 core
• Dual-core PowerVR® SGX544 3D GPU
• Three Video Input Port (VIP) modules
– Support for up to 10 multiplexed input ports
• General-Purpose Memory Controller (GPMC)
• Enhanced Direct Memory Access (EDMA)
controller
• 2-port gigabit ethernet (GMAC)
• Sixteen 32-Bit general-purpose timers
• 32-Bit MPU watchdog timer
• Five Inter-Integrated Circuit ( I2C™) ports
• HDQ™/ 1-Wire® interface
• SATA interface
• MediaLB® (MLB) subsystem
• Ten configurable UART/IrDA/CIR modules
• Four Multichannel Serial Peripheral Interfaces
(McSPI)
• Quad SPI (QSPI)
• Eight Multichannel Audio Serial Port (McASP)
modules
• SuperSpeed USB 3.0 dual-role device
• Three high-speed USB 2.0 dual-role devices
• Four Multimedia Card/Secure Digital/Secure Digital
Input Output interfaces ( MMC™/ SD®/SDIO)
• PCI-Express® 3.0 subsystems with two 5-Gbps
lanes
– One 2-lane gen2-compliant port
– or Two 1-lane gen2-compliant ports
• Dual Controller Area Network (DCAN) modules
– CAN 2.0B protocol
• Up to 247 General-Purpose I/O (GPIO) pins
• Real-Time Clock SubSystem (RTCSS)
• Device security features
– Hardware crypto accelerators and DMA
– Firewalls
– JTAG® lock
– Secure keys
– Secure ROM and boot
• Power, Reset, and Clock Management (PRCM)
• On-chip debug with CTools technology
• 28-nm CMOS technology
• 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA
(ABC)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

DRA755
DRA756, DRA755, DRA754, DRA752
DRA751, DRA750, DRA746, DRA745, DRA744
SPRS950F – DECEMBER 2015 – REVISED MAY 2019
www.ti.com
1.2 Applications
• Human-machine interface (HMI)
• Navigation
• Digital and analog radio
• Rear seat entertainment
• Multimedia playback
• Web browsing
• ADAS integration
1.3 Description
DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense
processing needs of the modern infotainment-enabled automobile experiences.
The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers
(ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming,
and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully
integrated mixed processor solution. The devices also combine programmable video processing with a
highly integrated peripheral set.
Programmability is provided by dual-core Arm® Cortex®-A15 RISC CPUs with Arm® Neon™ extension, TI
C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows
developers to keep control functions separate from other algorithms programmed on the DSP and
coprocessors, thus reducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor,
including C compilers and a debugging interface for visibility into source code.
The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.
PART NUMBER
Device Information(1)
PACKAGE
DRA756ABC
FCBGA (760)
DRA755ABC
FCBGA (760)
DRA754ABC
FCBGA (760)
DRA756ABC
FCBGA (760)
DRA755ABC
FCBGA (760)
DRA754ABC
FCBGA (760)
DRA752ABC
FCBGA (760)
DRA751ABC
FCBGA (760)
DRA750ABC
FCBGA (760)
(1) For more information, see Section 10, Mechanical, Packaging, and Orderable Information.
BODY SIZE
23.0 mm × 23.0 mm
23.0 mm × 23.0 mm
23.0 mm × 23.0 mm
23.0 mm × 23.0 mm
23.0 mm × 23.0 mm
23.0 mm × 23.0 mm
23.0 mm × 23.0 mm
23.0 mm × 23.0 mm
23.0 mm × 23.0 mm
2 Device Overview
Copyright © 2015–2019, Texas Instruments Incorporated
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Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity DRA756, DRA755, DRA754, DRA752 DRA751, DRA750, DRA746, DRA745, DRA744 SPRS950F – DECEMBER 2015 – REVISED MAY 2019 DRA75x, DRA74x Infotainment Ap plications Processor Silicon Revision 2 .0 1 Device Overview 1.1 Features 1 Architecture designed for infotainme nt applications • Video, image, and g raphics processing support – Full-HD video (1920 × 1080p, 60 fps) – Multi ple video input and video output – 2D and 3D graphics • Dual Arm® Cortex -A15 microprocessor subsystem • Up t o two C66x floating-point VLIW DSP – Fully object-code compatible with C67x and C64x+ – Up to thirty-two 16 x 16- Bit fixed-point multiplies per cycle Up to 2.5MB of on-chip L3 RAM • Lev el 3 (L3) and level 4 (L4) interconnect s • Two DDR2/DDR3/DDR3L memory interf ace (EMIF) modules – Supports up to D DR2-800 and DDR3-1066 – Up to 2GB sup ported per EMIF • Dual Arm® Cortex®-M4 Image Processing Units (IPU) • Up to two Embedded Vision En.
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