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DRA756 Dataheets PDF



Part Number DRA756
Manufacturers Texas Instruments
Logo Texas Instruments
Description Infotainment Applications Processor
Datasheet DRA756 DatasheetDRA756 Datasheet (PDF)

Product Folder Order Now Technical Documents Tools & Software Support & Community DRA756, DRA755, DRA754, DRA752 DRA751, DRA750, DRA746, DRA745, DRA744 SPRS950F – DECEMBER 2015 – REVISED MAY 2019 DRA75x, DRA74x Infotainment Applications Processor Silicon Revision 2.0 1 Device Overview 1.1 Features 1 • Architecture designed for infotainment applications • Video, image, and graphics processing support – Full-HD video (1920 × 1080p, 60 fps) – Multiple video input and video output – 2D and 3D.

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Product Folder Order Now Technical Documents Tools & Software Support & Community DRA756, DRA755, DRA754, DRA752 DRA751, DRA750, DRA746, DRA745, DRA744 SPRS950F – DECEMBER 2015 – REVISED MAY 2019 DRA75x, DRA74x Infotainment Applications Processor Silicon Revision 2.0 1 Device Overview 1.1 Features 1 • Architecture designed for infotainment applications • Video, image, and graphics processing support – Full-HD video (1920 × 1080p, 60 fps) – Multiple video input and video output – 2D and 3D graphics • Dual Arm® Cortex®-A15 microprocessor subsystem • Up to two C66x floating-point VLIW DSP – Fully object-code compatible with C67x and C64x+ – Up to thirty-two 16 x 16-Bit fixed-point multiplies per cycle • Up to 2.5MB of on-chip L3 RAM • Level 3 (L3) and level 4 (L4) interconnects • Two DDR2/DDR3/DDR3L memory interface (EMIF) modules – Supports up to DDR2-800 and DDR3-1066 – Up to 2GB supported per EMIF • Dual Arm® Cortex®-M4 Image Processing Units (IPU) • Up to two Embedded Vision Engines (EVEs) • IVA subsystem • Display subsystem – Display controller with DMA engine and up to three pipelines – HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant • Video Processing Engine (VPE) • 2D-graphics accelerator (BB2D) subsystem – Vivante® GC320 core • Dual-core PowerVR® SGX544 3D GPU • Three Video Input Port (VIP) modules – Support for up to 10 multiplexed input ports • General-Purpose Memory Controller (GPMC) • Enhanced Direct Memory Access (EDMA) controller • 2-port gigabit ethernet (GMAC) • Sixteen 32-Bit general-purpose timers • 32-Bit MPU watchdog timer • Five Inter-Integrated Circuit ( I2C™) ports • HDQ™/ 1-Wire® interface • SATA interface • MediaLB® (MLB) subsystem • Ten configurable UART/IrDA/CIR modules • Four Multichannel Serial Peripheral Interfaces (McSPI) • Quad SPI (QSPI) • Eight Multichannel Audio Serial Port (McASP) modules • SuperSpeed USB 3.0 dual-role device • Three high-speed USB 2.0 dual-role devices • Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces ( MMC™/ SD®/SDIO) • PCI-Express® 3.0 subsystems with two 5-Gbps lanes – One 2-lane gen2-compliant port – or Two 1-lane gen2-compliant ports • Dual Controller Area Network (DCAN) modules – CAN 2.0B protocol • Up to 247 General-Purpose I/O (GPIO) pins • Real-Time Clock SubSystem (RTCSS) • Device security features – Hardware crypto accelerators and DMA – Firewalls – JTAG® lock – Secure keys – Secure ROM and boot • Power, Reset, and Clock Management (PRCM) • On-chip debug with CTools technology • 28-nm CMOS technology • 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA (ABC) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRA756, DRA755, DRA754, DRA752 DRA751, DRA750, DRA746, DRA745, DRA744 SPRS950F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com 1.2 Applications • Human-machine interface (HMI) • Navigation • Digit.


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