Applications Processor. DRA710 Datasheet

DRA710 Processor. Datasheet pdf. Equivalent

DRA710 Datasheet
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Part DRA710
Description Infotainment Applications Processor
Feature DRA710; Product Folder Order Now Technical Documents Tools & Software Support & Community DRA710, DRA71.
Manufacture etcTI
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Texas Instruments DRA710
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
DRA710, DRA712
DRA714, DRA716, DRA718
SPRS960F – JUNE 2016 – REVISED MAY 2019
DRA71x Infotainment Applications Processor
1 Device Overview
1.1 Features
1
• Architecture designed for infotainment applications
• Video, image, and graphics processing support
– Full-HD video (1920 × 1080p, 60 fps)
– Multiple video input and video output
– 2D and 3D graphics
• Arm® Cortex®-A15 microprocessor subsystem
• C66x floating-point VLIW DSP
– Fully object-code compatible with C67x and
C64x+
– Up to thirty-two 16 × 16-bit fixed-point multiplies
per cycle
• Up to 512KB of on-chip L3 RAM
• Level 3 (L3) and Level 4 (L4) interconnects
• DDR3/DDR3L Memory Interface (EMIF) module
– Supports up to DDR-1333 (667 MHz)
– Up to 2GB across single chip select
• Dual Arm® Cortex®-M4 Image Processing Units
(IPU)
• IVA-HD subsystem
• Display subsystem
– Display controller With DMA engine and up to
three pipelines
– HDMI™ encoder: HDMI 1.4a and DVI 1.0
compliant
• 2D-graphics accelerator (BB2D) subsystem
– Vivante® GC320 core
• Video Processing Engine (VPE)
• Single-core PowerVR™ SGX544 3D GPU
• One Video Input Port (VIP) module
– Support for up to four multiplexed input ports
• General-Purpose Memory Controller (GPMC)
• Enhanced Direct Memory Access (EDMA)
controller
• 2-port gigabit ethernet (GMAC)
– Up to two external ports
• Sixteen 32-bit general-purpose timers
• 32-Bit MPU watchdog timer
• Six high-speed inter-integrated circuit (I2C) ports
• HDQ™/ 1-Wire® interface
• Ten configurable UART/IrDA/CIR modules
• Four Multichannel Serial Peripheral Interfaces
(McSPI)
• Quad SPI Interface (QSPI)
• Media Local Bus Subsystem (MLBSS)
• Eight Multichannel Audio Serial Port (McASP)
modules
• SuperSpeed USB 3.0 dual-role device
• High-speed USB 2.0 dual-role device
• High-speed USB 2.0 on-the-go
• Four MultiMedia Card/Secure Digital/Secure Digital
Input Output Interfaces ( MMC™/ SD®/SDIO)
• PCI Express® 3.0 subsystems with two 5-Gbps
lanes
– One 2-lane Gen2-compliant port
– or two 1-lane Gen2-compliant ports
• Dual Controller Area Network (DCAN) modules
– CAN 2.0B protocol
• MIPI® CSI-2 camera serial interface
• Up to 186 General-Purpose I/O (GPIO) pins
• Device security features
– Hardware crypto accelerators and DMA
– Firewalls
– JTAG lock
– Secure keys
– Secure ROM and boot
– Customer programmable keys
• Power, reset, and clock management
• On-chip debug with CTools technology
• 28-nm CMOS technology
• 17 mm × 17 mm, 0.65-mm pitch, 538-pin BGA
(CBD)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



Texas Instruments DRA710
DRA710, DRA712
DRA714, DRA716, DRA718
SPRS960F – JUNE 2016 – REVISED MAY 2019
www.ti.com
1.2 Applications
• Human-machine interface (HMI)
• Navigation
• Digital and analog radio
• Multimedia playback
• Automotive display audio systems
• Automotive entry navigation and multimedia
systems
• Automotive digital cluster systems
1.3 Description
The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can
be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.
The architecture is designed to deliver high-performance concurrencies for automotive applications in a
cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"),
DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics,
voice, HMI, multimedia and smartphone projection mode capabilities.
Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Arm Neon™ extensions and
a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions
separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity
of the system software.
Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers
and a debugging interface for visibility into source code execution.
Cryptographic acceleration is available in all devices. All other supported security features, including
support for secure boot, debug security and support for trusted execution environment are available on
High-Security (HS) devices. For more information about HS devices, contact your TI representative.
The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.
The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.
PART NUMBER
Device Information(1)
PACKAGE
DRA710CBD
FCBGA (538)
DRA712CBD
FCBGA (538)
DRA714CBD
FCBGA (538)
DRA716CBD
FCBGA (538)
DRA718CBD
FCBGA (538)
(1) For more information, see Section 9, Mechanical, Packaging, and Orderable Information.
BODY SIZE
17.0 mm × 17.0 mm
17.0 mm × 17.0 mm
17.0 mm × 17.0 mm
17.0 mm × 17.0 mm
17.0 mm × 17.0 mm
2 Device Overview
Copyright © 2016–2019, Texas Instruments Incorporated
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Product Folder Links: DRA710 DRA712 DRA714 DRA716 DRA718



Texas Instruments DRA710
www.ti.com
DRA710, DRA712
DRA714, DRA716, DRA718
SPRS960F – JUNE 2016 – REVISED MAY 2019
1.4 Functional Block Diagram
Figure 1-1 is functional block diagram for the device.
DRA71x
MPU
(1x Arm
Cortex–A15)
GPU
(1x SGX544 3D)
DSP
(1x C66x
Co-Processor)
IVA HD
1080p Video
Co-Processor
BB2D
(GC320 2D)
IPU1
(Dual Cortex–M4)
IPU2
(Dual Cortex–M4)
CAL CSI2 x1
Radio Accelerators
VCP x2
HD ATL
Display Subsystem
1xGFX / 3xVID
Blend / Scale
LCD2
LCD3
HDMI 1.4a
Secure Boot
Debug
Security
TEE
(HS devices)
EDMA
sDMA
MMU x2
VIP x1
VPE
High-Speed Interconnect
Spinlock
System
Timers x16
Mailbox x13
WDT
PWM SS x3
GPIO x8
KBD
HDQ
Connectivity
1x USB 3.0
Dual Mode FS/HS/SS
w/ PHY
2x USB 2.0
Dual Mode FS/HS
1x PHY, 1x ULPI
PCIe SS x2
MediaLB
MOST150
GMAC AVB
PRU-ICSS x2
Serial Interfaces
UART x10
QSPI
McSPI x4 McASP x8
DCAN x2
I2C x6
Program/Data Storage
512-KB
RAM with ECC
GPMC / ELM
(NAND/NOR/
Async)
EMIF x1
1x 32-bit
DDR3/DDR3L
256-KB ROM
MMC / SD x4
OCMC
DMM
Figure 1-1. DRA71x Block Diagram
intro-001
Copyright © 2016–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA710 DRA712 DRA714 DRA716 DRA718
Device Overview
3





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