Line Receiver. AM26LV32E-EP Datasheet

AM26LV32E-EP Receiver. Datasheet pdf. Equivalent

Part AM26LV32E-EP
Description Low-Voltage High-Speed Quadruple Differential Line Receiver
Feature AM26LV32E-EP www.ti.com SLLS948A – NOVEMBER 2008 – REVISED JULY 2013 LOW-VOLTAGE HIGH-SPEED QUADR.
Manufacture etcTI
Datasheet
Download AM26LV32E-EP Datasheet

AM26LV32E-EP www.ti.com SLLS948A – NOVEMBER 2008 – REVISED AM26LV32E-EP Datasheet
Recommendation Recommendation Datasheet AM26LV32E-EP Datasheet




AM26LV32E-EP
AM26LV32E-EP
www.ti.com
SLLS948A – NOVEMBER 2008 – REVISED JULY 2013
LOW-VOLTAGE HIGH-SPEED QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH ±15-kV IEC ESD PROTECTION
Check for Samples: AM26LV32E-EP
FEATURES
1
• Meets or Exceeds Standard TIA/EIA-422-B and
ITU Recommendation V.11
• Operates From a Single 3.3-V Power Supply
• ESD Protection for RS422 Bus Pins
– ±15-kV Human-Body Model (HBM)
– ±8-kV IEC61000-4-2, Contact Discharge
– ±15-kV IEC61000-4-2, Air-Gap Discharge
• Switching Rates up to 32 MHz
• Low Power Dissipation: 27 mW Typ
• Open-Circuit, Short-Circuit, and Terminated
Fail-Safe
• ±7-V Common-Mode Input Voltage Range With
±200-mV Sensitivity
• Accepts 5-V Logic Inputs With 3.3-V Supply
(Enable Inputs)
• Input Hysteresis: 35 mV Typ
• Pin-to-Pin Compatible With AM26C32,
AM26LS32
• Ioff Supports Partial-Power-Down Mode
Operation
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
• Controlled Baseline
• One Assembly/Test Site
• One Fabrication Site
• Available in Military (–55°C/125°C)
Temperature Range (1)
• Extended Product Life Cycle
• Extended Product-Change Notification
• Product Traceability
D PACKAGE
(TOP VIEW)
1B
1A
1Y
G
2Y
2A
2B
GND
1
2
3
4
5
6
7
8
16 VCC
15 4B
14 4A
13 4Y
12 G
11 3Y
10 3A
9 3B
(1) Additional temperature ranges are available – contact factory
DESCRIPTION/ORDERING INFORMATION
The AM26LV32E consists of quadruple differential line receivers with 3-state outputs. These differential receivers
have ±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact
Discharge) protection for RS422 bus pins.
This device is designed to meet TIA/EIA-422-B and ITU recommendation V.11 drivers with reduced supply
voltage. The device is optimized for balanced bus transmission at switching rates up to 32 MHz. The 3-state
outputs permit connection directly to a bus-organized system.
The AM26LV32E has an internal fail-safe circuitry that prevents the device from putting an unknown voltage
signal at the receiver outputs. In the open fail-safe, shorted fail-safe, and terminated fail-safe, a high state is
produced at the respective output.
This device is supported for partial-power-down applications using Ioff. Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The AM26LV32EM is characterized for operation from –55°C to 125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated



AM26LV32E-EP
AM26LV32E-EP
SLLS948A – NOVEMBER 2008 – REVISED JULY 2013
www.ti.com
TA
–55°C to 125°C
SOIC – D
Table 1. ORDERING INFORMATION
PACKAGE(1) (2)
ORDERABLE PART NUMBER
Tape and reel
AM26LV32EMDREP
TOP-SIDE MARKING
A26LV32EMP
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
FUNCTION TABLE(1)
(each receiver)
DIFFERENTIAL
INPUT
ENABLES
GG
VID 0.2 V
HX
XL
–0.2 V < VID < 0.2 V
H
X
X
L
VID –0.2 V
HX
XL
Open, shorted, or
terminated
H
X
X
L
X LH
OUTPUT
H
H
?
?
L
L
H
H
Z
(1) H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
LOGIC DIAGRAM (POSITIVE LOGIC)
G4
G 12
1A 2
1B 1
3 1Y
2A 6
2B 7
5 2Y
3A 10
3B 9
11 3Y
4A 14
4B 15
13 4Y
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Copyright © 2008–2013, Texas Instruments Incorporated
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