AM26LS33AM

AM26LS32AC, AM26LS32AI, AM26LS32AM AM26LS33AC, AM26LS33AM SLLS115G – OCTOBER 1980 – REVISED AUGUST 2023 AM26LS32Ax, AM26LS33Ax Quadruple Differential Line Receivers 1 Features AM26LS32A Devices meet or exceed the requirements of ANSI TIA/EIA-422-B, TIA/ EIA-423-B, and ITU recommendations V.10 and V.11 AM26LS32A Devices have ±7-V Common-mode range with ±200-mV sensitivity AM26LS33A Devices have ±15-V common-mode range with ±500-mV sensitivity Input hysteresis 50 mV typical Operate from a single 5-V supply Low-power Schottky circuitry 3-State outputs Complementary output-enable inputs Input impedance 12 kΩ minimum Open input fail-safe 2 Applications High-reliability automotive applications Factory automation ATM and cash counters Smart grids AC and servo motor drives 4 G G 12 1A 2 1B 1 3 1Y 6 2A 2B 7 5 2Y 3A 10 3B 9 11 3Y 14 4A 4B 15 13 4Y Copyright © 2016, Texas Instruments Incorporated Pin numbers are for D, N, NS, or PW packages only. Logic Diagram (Positive Logic) 3 Description The AM26LS32Ax and AM26LS33Ax devices are quadruple differential line receivers for balanced and unbalanced digital data transmission. The enable function is common to all four receivers and offers a choice of active-high or active-low input. The 3-state outputs permit connection directly to a bus-organized system. When the inputs are open, the fail-safe design makes sure the outputs always are high. Compared to the AM26LS32 and the AM26LS33, the AM26LS...