STATIC RAM. IDT7142LA Datasheet

IDT7142LA RAM. Datasheet pdf. Equivalent

Part IDT7142LA
Description HIGH SPEED 2K x 8 DUAL PORT STATIC RAM
Feature HIGH SPEED IDT7132SA/LA 2K x 8 DUAL PORT STATIC RAM IDT7142SA/LA LEAD FINISH (SnPb) ARE IN EOL P.
Manufacture Renesas
Datasheet
Download IDT7142LA Datasheet

Features ◆ High-speed access – Commercial: 20/25/35/55/100ns IDT7142LA Datasheet
HIGH SPEED IDT7132SA/LA 2K x 8 DUAL PORT STATIC RAM IDT71 IDT7142LA Datasheet
Recommendation Recommendation Datasheet IDT7142LA Datasheet




IDT7142LA
HIGH SPEED
IDT7132SA/LA
2K x 8 DUAL PORT
STATIC RAM
IDT7142SA/LA
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features
High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25ns (max.)
– Military: 25/35/55/100ns (max.)
Low-power operation
– IDT7132/42SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
– IDT7132/42LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
MASTER IDT7132 easily expands data bus width to 16-or-more
bits using SLAVE IDT7142
On-chip port arbitration logic (IDT7132 only)
BUSY output flag on IDT7132; BUSY input on IDT7142
Battery backup operation —2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC
packages
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Green parts available, see ordering information
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/OOL-I/O7L
BUSYL(1,2)
A10L
A0L
I/O
Control
I/O
Control
Address
Decoder
11
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
LOGIC
Address
Decoder
11
CER
OER
R/WR
I/OOR-I/O7R
m
BUSYR(1,2)
A10R
A0R
NOTES:
1. IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270.
IDT7142 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270.
2692 drw 01
©2018 Integrated Device Technology, Inc.
1
JULY 2018
DSC-2692/22



IDT7142LA
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7132/IDT7142 are high-speed 2K x 8 Dual-Port Static RAMs.
The IDT7132 is designed to be used as a stand-alone 8-bit Dual-Port RAM
or as a “MASTER” Dual-Port RAM together with the IDT7142 “SLAVE”
Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 16-or-more-bit memory system
applications results in full-speed, error-free operation without the need for
additional discrete logic.
Both devices provide two independent ports with separate control,
address, and l/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature, controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using CMOS high-performance technology, these
devices typically operate on only 325mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
The IDT7132/7142 devices are packaged in a 48-pin sidebraze or
plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and 48-lead flatpacks.
Military grade product is manufactured in compliance with the latest
revision of MIL-PRF-38535 QML, making it ideally suited to military
temperature applications demanding the highest level of performance
and reliability.
Pin Configurations(1,2,3)
CEL
R/WL
BUSYL
A10L
OEL
A0L
A1L
A2L
A3L
1 48
2 47
3 46
4 45
5 44
6
7
8
9
IDT7132
/7142
P or C
43
42
41
40
VCC
CER
R/WR
BUSYR
A10R
OER
A0R
A1R
A2R
A4L 10
39 A3R
A5L
A6L
A7L
A8L
11
12
P48(4)
&
38
37
13 C48(4) 36
14 35
A4R
A5R
A6R
A7R
A9L
I/O0L
I/O1L
I/O2L
I/O3L
15 48-Pin 34
16 DIP 33
17 Top 32
18 View(5) 31
19 30
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4L 20
I/O5L 21
29 I/O4R
28 I/O3R
I/O6L 22
27 I/O2R
I/O7L 23
26 I/O1R
GND 24
25 I/O0R ,
2692 drw 02
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. P48-1 package body is approximately .55 in x 2.43 in x .18 in.
C48-2 package body is approximately .62 in x 2.43 in x .15 in.
L48-1 package body is approximately .57 in x .57 in x .68 in.
F48-1 package body is approximately .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
INDEX
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
6 5 4 3 2 48 47 46 45 44 43
71
42
8 41
9 40
10
IDT7132/42L48 or F
39
11
L48(4)
38
12
&
F48(4)
37
13 36
48-Pin LCC/ Flatpack
14
Top View(5)
35
15 34
16 33
17 32
18 31
19 20 21 22 23 24 25 26 27 28 29 30
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
,
2692 drw 03
Capacitance(1) (TA = +25°C,f = 1.0MHz)
Symbol
Parameter
Conditions(2) Max. Unit
CIN Input Capacitance
VIN = 3dV
11 pF
COUT Output Capacitance
VOUT = 3dV
11 pF
NOTES:
2692 tbl 00
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 3V to 0V.
2





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