Gate Driver. DRV8703-Q1 Datasheet

DRV8703-Q1 Driver. Datasheet pdf. Equivalent

Part DRV8703-Q1
Description Automotive H-Bridge Gate Driver
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DRV8703-Q1
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
Reference
Design
DRV8702-Q1, DRV8703-Q1
SLVSDR9D – OCTOBER 2016 – REVISED DECEMBER 2018
DRV870x-Q1 Automotive H-Bridge Gate Driver
1 Features
1 AEC-Q100 Qualified for Automotive Applications
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
• Single H-Bridge Gate Driver
– Drives Four External N-Channel MOSFETs
– Supports 100% PWM Duty Cycle
• 5.5 to 45-V Operating Supply-Voltage Range
• Three Control-Interface Options
– PH/EN, Independent H-Bridge, and PWM
• Serial Interface for Configuration (DRV8703-Q1)
• Smart Gate Drive Architecture
– Adjustable Slew-Rate Control
• Independent Control of Each H-Bridge
• Supports 1.8-V, 3.3-V, and 5-V logic inputs
• Current-Shunt Amplifier
• Integrated PWM Current Regulation
• Low-Power Sleep Mode
• Protection Features
– Supply Undervoltage Lockout (UVLO)
– Charge-Pump Undervoltage (CPUV) Lockout
– Overcurrent Protection (OCP)
– Gate-Driver Fault (GDF)
– Thermal Shutdown (TSD)
– Watchdog Timer (DRV8703-Q1)
– Fault-Condition Output (nFAULT)
2 Applications
• Power Window Lift, Sunroof, Seats, Sliding Door,
Trunk and Tailgate
• Relay Replacement
– Application Report: SLVA837
– TI Design: TIDUCQ9
• Brushed-DC Pumps
A PH/EN, independent H-Bridge, or PWM interface
allows simple interfacing to controller circuits. An
internal sense amplifier provides adjustable current
control. Integrated Charge-Pump allows for 100%
duty cycle support and can be used to drive external
reverse battery switch.
Independent Half Bridge mode allows sharing of half
bridges to control multiple DC motors sequentially in
a cost-efficient way. The gate driver includes circuitry
to regulate the winding current using fixed off-time
PWM current chopping.
The DRV870x-Q1 devices include Smart Gate Drive
technology to remove the need for any external gate
components (resistors and Zener diodes) while
protecting the external FETs. The Smart Gate Drive
architecture optimizes dead time to avoid any shoot-
through conditions, provides flexibility in reducing
electromagnetic interference (EMI) with
programmable slew-rate control and protects against
any gate-short conditions. Additionally, active and
passive pulldowns are included to prevent any dv/dt
gate turn on.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DRV8702-Q1
DRV8703-Q1
VQFN (32)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
5.5 to 45 V
PH/EN or PWM
nSLEEP
VREF
Sense Output
nFAULT
DRV870x-Q1
H-Bridge Gate Driver
Shunt Amplifier
Current Regulation
Protection
Gate
Drive
FETs
Current
Sense
M
3 Description
The DRV870x-Q1 devices are small single H-bridge
gate drivers that use four external N-channel
MOSFETs targeted to drive a bidirectional brushed-
DC motor.
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



DRV8703-Q1
DRV8702-Q1, DRV8703-Q1
SLVSDR9D – OCTOBER 2016 – REVISED DECEMBER 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information .................................................. 7
6.5 Electrical Characteristics........................................... 7
6.6 SPI Timing Requirements ....................................... 12
6.7 Switching Characteristics ........................................ 12
6.8 Typical Characteristics ............................................ 14
7 Detailed Description ............................................ 19
7.1 Overview ................................................................. 19
7.2 Functional Block Diagram ....................................... 20
7.3 Feature Description................................................. 21
7.4 Device Functional Modes........................................ 39
7.5 Programming........................................................... 39
7.6 Register Maps ......................................................... 41
8 Application and Implementation ........................ 47
8.1 Application Information............................................ 47
8.2 Typical Application .................................................. 47
9 Power Supply Recommendations...................... 51
9.1 Bulk Capacitance Sizing ......................................... 51
10 Layout................................................................... 52
10.1 Layout Guidelines ................................................. 52
10.2 Layout Example .................................................... 52
11 Device and Documentation Support ................. 53
11.1 Documentation Support ........................................ 53
11.2 Related Links ........................................................ 53
11.3 Receiving Notification of Documentation Updates 53
11.4 Community Resources.......................................... 53
11.5 Trademarks ........................................................... 53
11.6 Electrostatic Discharge Caution ............................ 53
11.7 Glossary ................................................................ 53
12 Mechanical, Packaging, and Orderable
Information ........................................................... 54
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2018) to Revision D
Page
• Changed front page to remove second description................................................................................................................ 1
• Deleted Gate-Drive Current figure ......................................................................................................................................... 1
• Added SL2 pin to the continous shunt amplifier input pin voltage ......................................................................................... 6
• Added SL2 pin to the continous shunt amplifier input pin voltage ......................................................................................... 6
• Changed IN1 to IN1/PH and IN2 to IN2/EN .......................................................................................................................... 7
• Changed MODE typical pulldown resistance ........................................................................................................................ 8
• Added MODE typical pullup resistance .................................................................................................................................. 8
• Changed Wording in VDS Configuration section ................................................................................................................ 49
Changes from Revision B (March 2017) to Revision C
Page
• Changed the Features and Descriptions sections.................................................................................................................. 1
• Changed the type of the SL2 pin from O to I in the Pin Functions table................................................................................ 5
• Changed SPI parameter name conventions......................................................................................................................... 12
• Changed the VDS(OCP) from 0.86 V to 0.96 V in the OCP Threshold Voltage graph............................................................. 16
• Changed the I(CHOP) equation in the Current Regulation and Current Chopping Configuration sections ............................. 24
• Changed the current equation in the Amplifier Output (SO) section .................................................................................... 25
• Changed the description of the WD_EN bit in the IDRIVE and WD Field Descriptions table.............................................. 44
Changes from Revision A (November 2016) to Revision B
Page
• Added the R(VDRAIN) note to the External Components table ................................................................................................ 22
• Changed one resistor value from 32 kΩ to 65 kΩ in the MODE Pin Block Diagram ........................................................... 23
• Changed what happens when a fault condition is no longer present in the Overcurrent Protection (OCP) section............ 35
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Copyright © 2016–2018, Texas Instruments Incorporated
Product Folder Links: DRV8702-Q1 DRV8703-Q1





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