LVDS Converter. DS99R421 Datasheet

DS99R421 Converter. Datasheet pdf. Equivalent


Part DS99R421
Description 5-43 MHz FPD-Link LVDS to FPD-Link II LVDS Converter
Feature DS99R421 www.ti.com SNLS264D – JUNE 2007 – REVISED APRIL 2013 5-43 MHz FPD-Link LVDS (3 Data + 1 .
Manufacture etcTI
Datasheet
Download DS99R421 Datasheet


DS99R421 www.ti.com SNLS264D – JUNE 2007 – REVISED APRIL 2 DS99R421 Datasheet
Recommendation Recommendation Datasheet DS99R421 Datasheet




DS99R421
DS99R421
www.ti.com
SNLS264D – JUNE 2007 – REVISED APRIL 2013
5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC-
Balanced) Converter
Check for Samples: DS99R421
FEATURES
1
2 5 MHz–43 MHz Embedded Clock & DC-
Balanced Data Transmission (21 Total LVDS
Data Bits Plus 3 Low Speed LVCMOS Data
Bits)
• User Adjustable Pre-Emphasis Driving Ability
Through External Resistor on LVDS Outputs
and Capable to Drive up to 10 Meters Shielded
Twisted-Pair Cable
• Supports AC-Coupling Data Transmission
• 100Integrated Termination Resistor at LVDS
Input
• Power-Down Control
• Available @SPEED BIST to DS90UR124 to
Validate Link Integrity
• All LVCMOS Inputs & Control Pins Have
Internal Pulldown
• Schmitt Trigger Inputs on OS[2:0] to Minimize
Metastable Conditions
• Outputs Tri-Stated Through DEN
• On-Chip Filters for PLLs
• Power Supply Range 3.3V ± 10%
• Automotive Temperature Range 40°C to
+105°C
• Greater Than 8kV ESD Tolerance
• Meets ISO 10605 ESD and AEC-Q100
Compliance
DESCRIPTION
The DS99R421 converts a FPD-Link input with 4
non-DC Balanced LVDS (3 LVDS Data + LVDS
Clock) plus 3 over-sampled low speed control bits
into a single LVDS DC-balanced serial stream with
embedded clock information. This single serial stream
simplifies transferring the 24-bit bus over a single
differential pair of PCB traces and cable by
eliminating the skew problems between the 3 parallel
LVDS data inputs and LVDS clock paths. It saves
system cost by narrowing 4 LVDS pairs to 1 LVDS
pair that in turn reduce PCB layers, cable width,
connector size, and pins.
The DS99R421 incorporates a single serialized LVDS
signal on the high-speed I/O. Embedded clock LVDS
provides a low power and low noise environment for
reliably transferring data over a serial transmission
path. By optimizing the converter output edge rate for
the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost
signals over longer distances using lossy cables.
Internal DC balanced encoding is used to support
AC-Coupled interconnects.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated



DS99R421
DS99R421
SNLS264D – JUNE 2007 – REVISED APRIL 2013
Block Diagram
VODSEL
PRE
DEN
OS[2:0]
3
RxIN0-
RxIN0+
RxIN1-
RxIN1+
RxIN2-
RxIN2+
RxCLKIN-
RxCLKIN+
PWDNB
100:
100:
100:
21 Bits
Parallel
Data
100:
PLL
DS99R421
Standard 4 LVDS - to - 1 LVDS Tx ± Converter
Figure 1. Block Diagram
DOUT+
DOUT-
www.ti.com
Application Overview
OS[2:0]
3
LVDS
DATA0 100:
LVDS
DATA1
100:
LVDS
DATA2 100:
DOUT+
RIN+
DOUT- STP RIN-
(Up to 10 meters)
LVDS
CLK
100:
100:
Differential
PCB Traces
DS99R421
Figure 2. Typical Application Diagram
Rx - DESERIALIZER
2 Submit Documentation Feedback
Product Folder Links: DS99R421
Copyright © 2007–2013, Texas Instruments Incorporated







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