/ Deserializer. DS99R102 Datasheet

DS99R102 Deserializer. Datasheet pdf. Equivalent


Part DS99R102
Description 3-40MHz DC-Balanced 24-Bit LVDS Serializer / Deserializer
Feature DS99R101, DS99R102 www.ti.com SNLS240D – MARCH 2007 – REVISED APRIL 2013 DS99R101/DS99R102 3-40MH.
Manufacture etcTI
Datasheet
Download DS99R102 Datasheet


DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer DS99R102 Datasheet
DS99R101, DS99R102 www.ti.com SNLS240D – MARCH 2007 – REVI DS99R102 Datasheet
Recommendation Recommendation Datasheet DS99R102 Datasheet




DS99R102
DS99R101, DS99R102
www.ti.com
SNLS240D – MARCH 2007 – REVISED APRIL 2013
DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
Check for Samples: DS99R101, DS99R102
FEATURES
1
2 3 MHz–40 MHz Clock Embedded and DC-
Balancing 24:1 and 1:24 Data Transmissions
• User Selectable Clock Edge for Parallel Data
on Both Transmitter and Receiver
• Internal DC Balancing Encode/Decode –
Supports AC-Coupling Interface with No
External Coding Required
• Individual Power-Down Controls for Both
Transmitter and Receiver
• Embedded Clock CDR (Clock and Data
Recovery) on Receiver and No External Source
of Reference Clock Needed
• All Codes RDL (Random Data Lock) to Support
Live-Pluggable Applications
• LOCK Output Flag to Ensure Data Integrity at
Receiver Side
• Balanced TSETUP/THOLD Between RCLK and
RDATA on Receiver Side
• PTO (Progressive Turn-On) LVCMOS Outputs
to Reduce EMI and Minimize SSO Effects
• All LVCMOS Inputs and Control Pins Have
Internal Pulldown
• On-Chip Filters for PLLs on Transmitter and
Receiver
• 48-Pin TQFP Package
• Pure CMOS .35 μm Process
• Power Supply Range 3.3V ± 10%
• Temperature Range 0°C to +70°C
• 8 kV HBM ESD Tolerance
DESCRIPTION
The DS99R101/DS99R102 Chipset translates a 24-
bit parallel bus into a fully transparent data/control
LVDS serial stream with embedded clock information.
This single serial stream simplifies transferring a 24-
bit bus over PCB traces and cable by eliminating the
skew problems between parallel data and clock
paths. It saves system cost by narrowing data paths
that in turn reduce PCB layers, cable width, and
connector size and pins.
The DS99R101/DS99R102 incorporates LVDS
signaling on the high-speed I/O. LVDS provides a low
power and low noise environment for reliably
transferring data over a serial transmission path. By
optimizing the serializer output edge rate for the
operating frequency range EMI is further reduced.
Internal DC balanced encoding/decoding is used to
support AC-Coupled interconnects.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated



DS99R102
DS99R101, DS99R102
SNLS240D – MARCH 2007 – REVISED APRIL 2013
Block Diagram
DEN
VODSEL
REN
24
DIN
TRFB
DOUT+
DOUT-
RIN+
RIN-
24
ROUT
TCLK
TPWDNB
PLL
Timing
and
Control
RRFB
RPWDNB
PLL Timing
and
Control
Clock
Recovery
LOCK
RCLK
SERIALIZER ± DS99R101
DESERIALIZER ± DS99R102
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)
Supply Voltage (VDD)
LVCMOS/LVTTL Input Voltage
LVCMOS/LVTTL Output Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Duration
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 4 seconds)
Maximum Package Power Dissipation Capacity
Package De-rating:
DS99R101
DS99R102
ESD Rating (HBM)
48L TQFP
θJA
θJC
θJA
θJC
0.3V to +4V
0.3V to (VDD +0.3V)
0.3V to (VDD +0.3V)
0.3V to 3.9V
0.3V to 3.9V
10 ms
+150°C
65°C to +150°C
+260°C
1/θJA °C/W above +25°C
45.8 (4L(3)); 75.4 (2L(3)) °C/W
21.0°C/W
45.4 (4L(3)); 75.0 (2L(3))°C/W
21.1°C/W
±8 kV
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) JEDEC
2 Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS99R101 DS99R102







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