DS99R105

DS99R105, DS99R106 www.ti.com SNLS242D – MARCH 2007 – REVISED APRIL 2013 DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer Check for Samples: DS99R105, DS99R106 FEATURES 1 2 3 MHz–40 MHz Clock Embedded and DCBalancing 24:1 and 1:24 Data Transmissions Capable to Drive Shielded Twisted-Pair Cable User Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with no External Coding Required Individual Power-Down Controls for Both Transmitter and Receiver Embedded Clock CDR (Clock and Data Recovery) on Receiver and no External Source of Reference Clock Needed All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications LOCK Output Flag to Ensure Data Integrity at Receiver Side Balanced TSETUP/THOLD between RCLK and RDATA on Receiver Side PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects All LVCMOS Inputs and Control Pins have Internal Pulldown On-Chip Filters for PLLs on Transmitter and Receiver Integrated 100Ω Input Termination on Receiver 4 mA Receiver Output Drive 48-Pin TQFP and 48-Pin WQFN Packages Pure CMOS .35 μm Process Power Supply Range 3.3V ± 10% Temperature Range 0°C to +70°C 8 kV HBM ESD Tolerance DESCRIPTION The DS99R105/DS99R106 Chipset translates a 24bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single seri...