Switching Regulator. LM26001B Datasheet

LM26001B Regulator. Datasheet pdf. Equivalent

Part LM26001B
Description 1.5A Switching Regulator
Feature LM26001B www.ti.com SNVS491B – MAY 2007 – REVISED APRIL 2013 LM26001B 1.5A Switching Regulator wi.
Manufacture etcTI
Datasheet
Download LM26001B Datasheet

LM26001B 1.5A Switching Regulator with High Efficiency Sleep LM26001B Datasheet
LM26001B www.ti.com SNVS491B – MAY 2007 – REVISED APRIL 20 LM26001B Datasheet
Recommendation Recommendation Datasheet LM26001B Datasheet




LM26001B
LM26001B
www.ti.com
SNVS491B – MAY 2007 – REVISED APRIL 2013
LM26001B 1.5A Switching Regulator with High Efficiency Sleep Mode
Check for Samples: LM26001B
FEATURES
1
2 High Efficiency Sleep Mode
• 40 µA Typical Iq in Sleep Mode
• 10 µA Typical Iq in Shutdown Mode
• 3.0V Minimum Input Voltage
• 4.0V to 18V Continuous Input Range
• 2.0% Reference Accuracy
• Cycle-by-Cycle Current Limit
• Adjustable Frequency (150 kHz to 500 kHz)
• Synchronizable to an External Clock
• Power Good Flag
• Forced PWM Function
• Adjustable Soft-Start
• HTSSOP-16 Exposed Pad Package
• Thermal Shut Down
APPLICATIONS
• Automotive Telematics
• Navigation Systems
• In-Dash Instrumentation
• Battery Powered Applications
• Stand-by Power for Home Gateways/Set-Top
Boxes
DESCRIPTION
The LM26001B is a switching regulator designed for
the high efficiency requirements of applications with
stand-by modes. The device features a low-current
sleep mode to maintain efficiency under light-load
conditions and current-mode control for accurate
regulation over a wide input voltage range. Quiescent
current is reduced to 10 µA typically in shutdown
mode and less than 40 µA in sleep mode. Forced
PWM mode is also available to disable sleep mode.
The LM26001B can deliver up to 1.5A of continuous
load current with a fixed current limit, through the
internal N-channel switch. The part has a wide input
voltage range of 4.0V to 18V and can operate with
input voltages as low as 3V during line transients.
Operating frequency is adjustable from 150 kHz to
500 kHz with a single resistor and can be
synchronized to an external clock.
Other features include Power good, adjustable soft-
start, enable pin, input under-voltage protection, and
an internal bootstrap diode for reduced component
count.
Typical Application Circuit
VIN
C1
R4
VDD
EN
SYNC
R6
C5
R3
1 VIN
2
VIN
12
VBIAS
16
SW
3 PGOOD
15
SW
4
EN
14
BOOT
11 LM26001B 7
SYNC
FB
5
SS
COMP 6
9
FREQ
13
VDD
10
FPWM
EP
8
GND
17
L
C4 D1
C8
C3 R5
VOUT
+
R1 C6
R2
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated



LM26001B
LM26001B
SNVS491B – MAY 2007 – REVISED APRIL 2013
Connection Diagram
Top View
VIN 1
VIN 2
PGOOD 3
EN 4
SS 5
COMP 6
FB 7
GND 8
Exposed Pad
Connect to GND
16 SW
15 SW
14 BOOT
13 VDD
12 VBIAS
11 SYNC
10 FPWM
9 FREQ
Figure 1. 16-Lead Exposed Pad HTSSOP Package
See Package Number PWP0016A
www.ti.com
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
EP
Pin Name
VIN
VIN
PGOOD
EN
SS
COMP
FB
GND
FREQ
FPWM
SYNC
VBIAS
VDD
BOOT
SW
SW
EP
Pin Descriptions
Description
Power supply input
Power supply input
Power Good pin. An open drain output which goes high when the output voltage is greater than 92% of
nominal.
Enable is an analog level input pin. When pulled below 0.8V, the device enters shutdown mode.
Soft-start pin. Connect a capacitor from this pin to GND to set the soft-start time.
Compensation pin. Connect to a resistor capacitor pair to compensate the control loop.
Feedback pin. Connect to a resistor divider between Vout and GND to set output voltage.
Ground
Frequency adjust pin. Connect a resistor from this pin to GND to set the operating frequency.
FPWM is a logic level input pin. For normal operation, connect to GND. When pulled high, sleep mode
operation is disabled.
Frequency synchronization pin. Connect to an external clock signal for synchronized operation. SYNC
must be pulled low for non-synchronized operation.
Connect to an external 3V or greater supply to bypass the internal regulator for improved efficiency. If
not used, VBIAS should be tied to GND.
The output of the internal regulator. Bypass with a minimum 1.0 µF capacitor.
Bootstrap capacitor pin. Connect a 0.1µF minimum ceramic capacitor from this pin to SW to generate
the gate drive bootstrap voltage.
Switch pin. The source of the internal N-channel switch.
Switch pin. The source of the internal N-channel switch.
Exposed Pad thermal connection. Connect to GND.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Product Folder Links: LM26001B
Copyright © 2007–2013, Texas Instruments Incorporated





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