Switching Controller. LM2642 Datasheet

LM2642 Controller. Datasheet pdf. Equivalent


Part LM2642
Description Two-Phase Synchronous Step-Down Switching Controller
Feature LM2642 www.ti.com SNVS203I – MAY 2002 – REVISED APRIL 2013 LM2642 Two-Phase Synchronous Step-Down.
Manufacture etcTI
Datasheet
Download LM2642 Datasheet


LM2642 Two-Phase Synchronous Step-Down Switching Controller LM2642 Datasheet
LM2642 www.ti.com SNVS203I – MAY 2002 – REVISED APRIL 2013 LM2642 Datasheet
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LM2642
LM2642
www.ti.com
SNVS203I – MAY 2002 – REVISED APRIL 2013
LM2642 Two-Phase Synchronous Step-Down Switching Controller
Check for Samples: LM2642
FEATURES
1
2 Two Synchronous Buck Regulators
• 180° Out of Phase Operation
• 4.5V to 30V Input Range
• Power Good Function Monitors Ch.1
• 37µA Shutdown Current
• 0.04% (typical) Line and Load Regulation Error
• Current Mode Control With or Without a Sense
Resistor
• Independent Enable/Soft-start Pins Allow
Simple Sequential Startup Configuration.
• Configurable for Single Output Parallel
Operation. (See Figure 3).
• Adjustable Cycle-by-Cycle Current Limit
• Input Under-voltage Lockout
• Output Over-voltage Latch Protection
• Output Under-voltage Protection with Delay
• Thermal Shutdown
• Self Discharge of Output Capacitors When the
Regulator is OFF
• TSSOP package
APPLICATIONS
• Embedded Computer Systems
• High End Gaming Systems
• Set-top Boxes
• WebPAD
DESCRIPTION
The LM2642 consists of two current mode
synchronous buck regulator controllers with a
switching frequency of 300kHz.
The two switching regulator controllers operate 180°
out of phase. This feature reduces the input ripple
RMS current, thereby significantly reducing the
required input capacitance. The two switching
regulator outputs can also be paralleled to operate as
a dual-phase single output regulator.
The output of each channel can be independently
adjusted from 1.3 to VIN• maximum duty cycle. An
internal 5V rail is also available externally for driving
bootstrap circuitry.
Current-mode feedback control assures excellent line
and load regulation and a wide loop bandwidth for
excellent response to fast load transients. Current is
sensed across either the Vds of the top FET or
across an external current-sense resistor connected
in series with the drain of the top FET. Current limit is
independently adjustable for each channel.
The LM2642 features analog soft-start circuitry that is
independent of the output load and output
capacitance. This makes the soft-start behavior more
predictable and controllable than traditional soft-start
circuits.
A PGOOD1 pin is provided to monitor the dc output
of channel 1. Over-voltage protection is available for
both outputs. A UV-Delay pin is also available to
allow delayed shut off time for the IC during an output
under-voltage event.
BLOCK DIAGRAM
VIN
4.5V-30V
UV_Delay
PGOOD1
SS/ON1
SS/ON2
LM2642
H
L
H
L
VOUT1
1.3V-27V
VOUT2
1.3V-27V
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2013, Texas Instruments Incorporated



LM2642
LM2642
SNVS203I – MAY 2002 – REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
CONNECTION DIAGRAM
TOP VIEW
1 KS1
2 ILIM1
3 COMP1
4 FB1
5 PGOOD1
6 UVDELAY
7 VLIN5
8 SGND
9 ON/SS1
10 ON/SS2
11 FB2
12 COMP2
13 ILIM2
14 KS2
RSNS1 28
SW1 27
HDRV1 26
CBOOT1 25
VDD1 24
LDRV1 23
VIN 22
PGND 21
LDRV2 20
VDD2 19
CBOOT2 18
HDRV2 17
SW2 16
RSNS2 15
Figure 1. 28-Lead TSSOP
PIN DESCRIPTIONS
KS1 (Pin 1) The positive (+) Kelvin sense for the internal current sense amplifier of Channel 1. Use a separate
trace to connect this pin to the current sense point. It should be connected to VIN as close as possible to
the node of the current sense resistor. When no current-sense resistor is used, connect as close as
possible to the drain node of the upper MOSFET.
ILIM1 (Pin 2) Current limit threshold setting for Channel 1. It sinks a constant current of 10 µA, which is
converted to a voltage across a resistor connected from this pin to VIN. The voltage across the resistor is
compared with either the VDS of the top MOSFET or the voltage across the external current sense
resistor to determine if an over-current condition has occurred in Channel 1.
COMP1 (Pin 3) Compensation pin for Channel 1. This is the output of the internal transconductance amplifier.
The compensation network should be connected between this pin and the signal ground, SGND (Pin 8).
FB1 (Pin 4) Feedback input for channel 1. Connect to VOUT through a voltage divider to set the channel 1
output voltage.
PGOOD1 (Pin 5) An open-drain power-good output for Channel 1. It is 'LOW' (low impedance to ground)
whenever the output voltage of Channel 1 falls outside of a +15% to -9% window. PGOOD1 stays latched
in a 'LOW' state during OVP or UVP on either channel. It will recover to a 'HIGH' state (high impedance to
ground) after a Channel 1 output under-voltage event (<91%) when the output returns to within 6% of its
nominal value. See Operation Descriptions for details.
UV_DELAY (Pin 6) A capacitor from this pin to ground sets the delay time for UVP. The capacitor is charged
from a 5µA current source. When UV_DELAY charges to 2.3V (typical), the system immediately latches
off. Connecting this pin to ground will disable the output under-voltage protection.
VLIN5 (Pin 7) The output of an internal 5V LDO regulator derived from VIN. It supplies the internal bias for the
chip and supplies the bootstrap circuitry for gate drive. Bypass this pin to signal ground with a minimum of
4.7µF capacitor.
SGND (Pin 8) The ground connection for the signal-level circuitry. It should be connected to the ground rail of the
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Copyright © 2002–2013, Texas Instruments Incorporated







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