Document
PIC18F27/47/57Q43
28/40/44/48-Pin, Low-Power, High-Performance Microcontroller with XLP Technology
Introduction
The PIC18-Q43 microcontroller family is available in 28/40/44/48-pin devices for real-time control applications. This family features a 12-bit Analog-to-Digital Converter with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advanced capacitive touch sensing, averaging, filtering, oversampling and threshold comparison. This family showcases a new 16-bit Pulse-Width Modulator (PWM) module which provides dual independent outputs on the same time base. Additional features include vectored interrupt controller with fixed latency for handling interrupts, system bus arbiter, Direct Memory Access (DMA) capabilities, Universal Asynchronous Receiver-Transmitter (UART) with support for asynchronous, Digital Multiplex (DMX), Digital Addressable Lighting Interface (DALI) and Local Interconnect Network (LIN) protocols, Serial Peripheral Interface (SPI), I2C, memory features like Memory Access Partition (MAP) to support users in data protection and bootloader applications, and Device Information Area (DIA), which stores factory calibration values to help improve temperature sensor accuracy.
PIC18-Q43 Family Types
Table 1. Devices Included in This Data Sheet
PIC18F27Q43 128k 8192 1024 Y/Y 25/Y 3/4 3/3 3 1 3 8 24 1 2/1 1 2/1 4/1 6 Y Y Y Y Y PIC18F47Q43 128k 8192 1024 Y/Y 36/Y 3/4 3/3 3 1 3 8 35 1 2/1 1 2/1 4/1 6 Y Y Y Y Y PIC18F57Q43 128k 8192 1024 Y/Y 44/Y 3/4 3/3 3 1 3 8 43 1 2/1 1 2/1 4/1 6 Y Y Y Y Y
Device Program Memory Flash
(bytes) Data SRAM
(bytes) Data EEPROM
(bytes) Memory Access Partition/ Device Information Area
I/O Pins/ Peripheral Pin Select 8-Bit Timer with HLT/
16-Bit Timers 16-Bit Dual PWM/
CCP Complementary Waveform
Generator Signal Measurement Timer
Numerically Controlled Oscillator
Configurable Logic Cell 12-Bit ADCC (channels)
8-Bit DAC Comparator/ Zero-Cross Detect High-Low Voltage Detect
SPI/I2C UART/ UART with Protocol Support Direct Memory Access (DMA) Windowed Watchdog Timer 16-Bit CRC with Scanner Vectored Interrupts Peripheral Module Disable Temperature Indicator
© 2019-2023 Microchip Technology Inc.
and its subsidiaries
Data Sheet
DS40002147G-page 1
Table 2. Devices not Included in This Data Sheet
PIC18F27/47/57Q43
Device Program Memory Flash
(bytes) Data SRAM
(bytes) Data EEPROM
(bytes) Memory Access Partition/ Device Information Area
I/O Pins/ Peripheral Pin Select 8-Bit Timer with HLT/
16-Bit Timers 16-Bit Dual PWM/
CCP Complementary Waveform
Generator Signal Measurement Timer
Numerically Controlled Oscillator
Configurable Logic Cell 12-Bit ADCC (channels)
8-Bit DAC Comparator/ Zero-Cross Detect High-Low Voltage Detect
SPI/I2C UART/ UART with Protocol Support Direct Memory Access (DMA) Windowed Watchdog Timer 16-Bit CRC with Scanner Vectored Interrupts Peripheral Module Disable Temperature Indicator
PIC18F25Q43 32k 2048 1024 Y/Y 25/Y 3/4 3/3 3 1 3 8 24 1 2/1 1 2/1 4/1 6 Y Y Y Y Y PIC18F26Q43 64k 4096 1024 Y/Y 25/Y 3/4 3/3 3 1 3 8 24 1 2/1 1 2/1 4/1 6 Y Y Y Y Y PIC18F45Q43 32k 2048 1024 Y/Y 36/Y 3/4 3/3 3 1 3 8 35 1 2/1 1 2/1 4/1 6 Y Y Y Y Y PIC18F46Q43 64k 4096 1024 Y/Y 36/Y 3/4 3/3 3 1 3 8 35 1 2/1 1 2/1 4/1 6 Y Y Y Y Y PIC18F55Q43 32k 2048 1024 Y/Y 44/Y 3/4 3/3 3 1 3 8 43 1 2/1 1 2/1 4/1 6 Y Y Y Y Y PIC18F56Q43 64k 4096 1024 Y/Y 44/Y 3/4 3/3 3 1 3 8 43 1 2/1 1 2/1 4/1 6 Y Y Y Y Y
Features
• C Compiler Optimized RISC Architecture • Operating Speed:
– DC – 64 MHz clock input – 62.5 ns minimum instruction cycle • Six Direct Memory Access (DMA) Controllers: – Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR
spaces – User programmable source and destination sizes – Hardware and software triggered data transfers • Vectored Interrupt Capability: – Selectable high/low priority – Fixed interrupt latency of three instruction cycles – Programmable vector table base address – Backwards compatible with previous interrupt capabilities • 127-Level Deep Hardware Stack • Low-Current Power-on Reset (POR) • Configurable Power-up Timer (PWRT) • Brown-out Reset (BOR) • Low-Power BOR (LPBOR) Option • Windowed Watchdog Timer (WWDT): – Watchdog Reset on too long or too short interval between watchdog clear events – Variable prescaler selection – Variable window size selection
Memory
• Up to 128 KB of Program Flash Memory • Up to 8 KB of Data SRAM Memory • 1024 Bytes Data EEPROM • Memory Access Partition: The Program Flash Memory can be partitioned into:
– Application Block – Boot Block – Storage Area Flash (SAF) Block
© 2019-2023 Microchip Technology Inc.
and its subsidiaries
Data Sheet
DS40002147G-page 2
PIC18F27/47/57Q43
• Programmable Code Protection and Write Protection • Device Information Area (DIA) Stores:
– Temperature indicator factory calibrated data – Fixed Voltage Reference measurement data – Microchip unique identifier • Device Character.