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GC5330 Dataheets PDF



Part Number GC5330
Manufacturers Texas Instruments
Logo Texas Instruments
Description Wideband Transmit-Receive Digital Signal Processors
Datasheet GC5330 DatasheetGC5330 Datasheet (PDF)

Not Recommended For New Designs www.ti.com GC5330 GC5337 SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011 Wideband Transmit-Receive Digital Signal Processors Check for Samples: GC5330, GC5337 FEATURES 1 • Integrated Transmit and Receive Digital IF Solution • Up to 4 TX, 8 RX, Plus DPD Feedback • TX-Transmit Includes DUC, CFR, DPD, TX Equalizer, and Bulk Upconverter • 62-MHz TX Signal Bandwidth With Fifth-Order DPD Correction • CFR: 6-dB PAR for WCDMA, 7-db LTE Signals With EVM Meeting 3GPP Sp.

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Not Recommended For New Designs www.ti.com GC5330 GC5337 SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011 Wideband Transmit-Receive Digital Signal Processors Check for Samples: GC5330, GC5337 FEATURES 1 • Integrated Transmit and Receive Digital IF Solution • Up to 4 TX, 8 RX, Plus DPD Feedback • TX-Transmit Includes DUC, CFR, DPD, TX Equalizer, and Bulk Upconverter • 62-MHz TX Signal Bandwidth With Fifth-Order DPD Correction • CFR: 6-dB PAR for WCDMA, 7-db LTE Signals With EVM Meeting 3GPP Specs; Configurable for All Major Wireless Infrastructure Standards • DPD: Memory Compensation, Typical ACLR Improvement of 20 dB or More • RX-Receive Includes DC-Offset Cancellation, Front-End and Back-End AGC, Bulk Downconverter, RX Equalizer, I/Q Imbalance Correction, DDC • 4 DDUCs, 1–12 Channels per DDUC, Each DDUC Can Be Programmed to TX or RX, at a Common Resampler Rate – Multimode Support • Seamless Interface to TI High-Speed Data Converters • 4 TX Aggregate Output to DACs up to 930 MSPS Complex • 8 RX Aggregate Input From ADCs up to 1.24 GSPS Real • Supports Envelope Tracking Techniques • 16-Tap (Complex) RX Equalizers • Two 4K Complex Word Capture Buffers for Signal Analysis, Adaptive Filtering, and DPD Algorithms • TMS320C6748 DPD Optimization Software • 1.1-V Core, 3.3-V I/O CMOS, 1.8-V I/O LVDS • Power Consumption, 3.5 W Typical • 484-Ball TE-PBGA Package, 23 mm × 23 mm APPLICATIONS • Multi-Standard Base Stations • 3GPP (LTE, W-CDMA, TDS-CDMA) • MC-GSM • WiMAX and WiBro (OFDMA) • Multi-Carrier Power Amplifiers (MCPAs) • Wireless Infrastructure Repeaters • Up to 4 × 4 MIMO DESCRIPTION The GC533x is a wideband transmit and receive signal processor that includes digital downconverter / upconverter (DDUC), transmit, receive, and capture buffer blocks. The transmit path includes crest factor reduction (CFR), digital predistortion (DPD) and associated feedback path, complex equalization, and bulk upconversion. The receive path includes wideband and narrowband automatic gain control (AGC), bulk downconversion, complex equalization, and I/Q imbalance correction. The DDUC section consists of four identical DDUC blocks, each supporting up to 12 channels. Each channel has independent fractional resamplers and NCOs to enable flexible carrier configurations. Multi-mode/multi-standard operation can be supported by configuring the individual DDUC blocks to different filtering and oversampling scenarios. C6748 DSP DAC3484 DAC I/Q TRF3703/3720 I/Q Mod I/Q Mod Complex TX PA PA DAC I/Q I/Q Mod I/Q Mod PA PA Baseband Data GC533x DUC-CFR DPD DDC ADS61B49 FB ADC ADS62P49 RX ADC RX ADC ADS62P49 RX ADC RX ADC Mixer/BPF SW Subsampled Feedback Mixer/BPF Mixer/BPF LNA Real RX LNA Mixer/BPF Mixer/BPF LNA LNA Real RX B0441-01 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. © 2010–2011, Texas Instruments Incorporated GC5330 GC5337 Not Recommended For New Designs SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (Continued) The CFR block reduces the peak-to-average ratio (PAR) of the digital transmit signals, such as those used in third-generation (3G) code division multiple access (CDMA) and orthogonal frequency-division multiple-access (OFDMA) applications. The DPD path with a 310-MHz DPD clock can be configured to support one antenna at 62 MHz, two antennas at 62 MHz each, or four antennas at 31 MHz each, all with an associated 5× DPD expansion bandwidth. The GC533x DPD processor reduces power amplifier (PA) nonlinearity, e.g., as measured by adjacent-channel leakage ratio (ACLR), by over 20 dB. By reducing the PAR of the digital signal and the PA nonlinearity, the operational efficiency of follow-on power amplifiers can be substantially improved. A higher DPD bandwidth is possible with reduced DPD performance. Several architectures that provide performance and cost optimization are listed in Table 1 Figure TX Antenna Figure 1 2-62 {74} MHz Figure 2 2-62 {74} MHz Figure 3 2-62 {74} MHz Figure 4 2-62 {74} MHz Figure 5 4-31 {37} MHz Table 1. Sample Configurations for GC5330 {GC5337} DPD Bandwidth 310 {370} MHz 310 {370} MHz 310 {370} MHz 310 {370} MHz 155 {185} MHz ET Support 2-envelope tracking Feedback RX Antenna Other 2 typical at 250 Subsampled real Msps, up to 4 at 250 Msps Lower-cost 2-antenna so.


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