GC5328

GC5328 www.ti.com SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009 GC5328 Low-Power Wideband Digital Predistortion Transmit Processor Check for Samples: GC5328 FEATURES 1 Integrated DUC, CFR, and DPD Solution 20-MHz Max. Signal Bandwidth, Based on Max. DPD Clock of 200 Mhz, Fifth-Order Correction DUC: Up to 12 CDMA2000/TDSCDMA, 4 W-CDMA, 2–10 MHz or 1–20 MHz OFDMA Carriers CFR: Typically Meets 3GPP TS 25.141 < 6.5 dB PAR, < 8.5 dB PAR for OFDMA Signals DPD: Short-Term Memory Compensation, Typical ACLR Improvement > 20 dB GC5328IZER PBGA Package, 23 mm × 23 mm 1.2-V Core, 1.8-V HSTL, 3.3-V I/O 2.5-W Typical Power Consumption TMS320C6727 DPD Optimization Software Supports Direct Interface to TI High-Speed Data Converters APPLICATIONS 3 GPP (W-CDMA) Base Stations 3 GPP2 (CDMA2000) Base Stations WiMAX, WiBRO, and LTE (OFDMA) Base Stations Multicarrier Power Amplifiers (MCPAs) BB Data GC5328 DAC I/Q DAC DUC-CFR-DPD ADC I/Q Modulator LO Mixer Attenuator 0–31.5 dB HPA LPA Attenuator 0–31.5 dB Host Control Interface 'C6727 DSP Figure 1. GC5328 System Block Diagram B0278-03 DESCRIPTION The GC5328 is a lower-power version of the GC5322 wideband digital predistortion transmit processor. The GC5328 includes a digital upconverter (DUC) block, a crest factor reduction (CFR) block, a digital predistortion (DPD) block, feedback (FB) block, and capture buffer (CB) blocks. The GC5328 GPP block receives the interleaved IQ data from the baseband inp...