Document
Product Folder
Order Now
Technical Documents
Tools & Software
Support & Community
Reference Design
DLPC3432
DLPS108C – FEBRUARY 2018 – REVISED JUNE 2019
DLPC3432 Display Controller
1 Features
•1 DLP230GP (.23 qHD) DMD display controller – Supports input resolutions up to 720p – Low-power DMD interface with interface training
• Input frame rates up to 120 Hz • 24-Bit, input pixel interface including:
– Parallel or BT656, interface protocols – Pixel clock up to 150 MHz – Multiple input pixel data format options • Pixel data processing including: – IntelliBright™ suite of image processing
algorithms – Content adaptive illumination control – Local area brightness boost – 1-D keystone correction – Color coordinate adjustment – Active power management processing • External flash support • Embedded frame memory (eDRAM) • System features including: – I2C control of device configuration – Programmable LED current control – One frame latency
2 Applications
• Smart phone, tablet, laptop • Battery-powered mobile accessory • Wearable (near-eye) display • Smart home display • Smart speaker
3 Description
The DLPC3432 digital controller, part of the DLP230GP (.23 qHD) chipset, supports reliable operation of the DLP230GP digital micromirror device (DMD). The DLPC3432 controller provides a convenient, multi-functional interface between user electronics and the DMD, enabling small form factor and low power display applications.
Visit the getting started with TI DLP®PicoTM display technology page to learn how to get started with the DLP230GP chipset.
The DLP230GP chipset includes established resources to help the user accelerate the design cycle, which include production ready optical modules, optical modules manufactures, and design houses.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DLPC3432
NFBGA (176)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
Simplified Schematic
Projector Module Electronics
+ BAT ± DC Supplies
2.3 V ± 5.5 V
Other Supplies
1.8 V PROJ_ON
Flash
HDMI Keypad
Video Front End / System
Controller
HOST_IRQ DSI(10)
Parallel I/F 28 I2C
Included in DLP® Chip Set Non-TI Components
1.8 V 1.1 V
1.8 V VSPI
SYSPWR 1.8 V
1.1 V Reg
PROJ_ON
1.1 V
L3
1.8 V Focus Stepper Motor
GPIO_8(Normal Park)
VCC Flash SPI_0
SPI_1 PARKZ
SPI(4) RESETZ
INTZ LED SEL(2)
RC_CHARGE
CMP_PWM
DLPC3432
DLPC200x
L1
Current Sense
L2
RED GREEN BLUE
BIAS, RST, OFS 3
eDRAM
CMP_OUT
Illumination Optics
VCC_INTF
Spare R/W GPIO
Thermistor
Sub-LVDS DATA (18)
0.23 qHD DMD
VIO VCORE
CTRL
Focus Motor Position Sensor
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLPC3432
DLPS108C – FEBRUARY 2018 – REVISED JUNE 2019
www.ti.com
Table of Contents
1 Features .................................................................. 1 2 Applications ........................................................... 1 3 Description ............................................................. 1 4 Revision History..................................................... 2 5 Pin Configuration and Functions ......................... 3 6 Specifications....................................................... 14
6.1 Absolute Maximum Ratings .................................... 14 6.2 ESD Ratings............................................................ 14 6.3 Recommended Operating Conditions..................... 15 6.4 Thermal Information ................................................ 15 6.5 Electrical Characteristics Over Recommended
Operating Conditions ............................................... 16 6.6 Electrical Characteristics......................................... 17 6.7 Internal Pullup and Pulldown Characteristics.......... 19 6.8 High-Speed Sub-LVDS Electrical Characteristics... 19 6.9 Low-Speed SDR Electrical Characteristics............. 20 6.10 System Oscillators Timing Requirements ............. 21 6.11 Power-Up and Reset Timing Requirements ......... 21 6.12 Parallel Interface Frame Timing Requirements .... 22 6.13 Parallel Interface General Timing Requirements .. 23 6.14 BT656 Interface General Timing Requirements ... 24 6.15 DSI Host Timing Requirements .......................... 24 6.16 Flash Interface Timing Requirements ................... 25 7 Parameter Measurement Information ................ 26 7.1 HOST_IRQ Usage Model ....................................... 26 7.2 Input Source............................................................ 27 8 Detailed Description ............................................ 30
8.1 Overview ................................................................. 30 8.2 Functional Block Diagram ....................................... 30 8.3 Feature Description..............