DAC34SH84

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference Design DAC34SH84 SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) 1 Features 1 Low Power: 1.8 W at 1.5 GSPS, Full Operating Condition Multi-DAC Synchronization Selectable 2×, 4×, 8×, 16× Interpolation Filter – Stop-Band Attenuation > 90 dBc Flexible On-Chip Complex Mixing – Two Independent Fine Mixers With 32-Bit NCOs – Power-Saving Coarse Mixers: ±n × fS / 8 High-Performance, Low-Jitter Clock-Multiplying PLL Digital I and Q Correction – Gain, Phase and Offset Digital Inverse Sinc Filters 32-Bit DDR Flexible LVDS Input Data Bus – 8-Sample Input FIFO – Supports Data Rates up to 750 MSPS – Data Pattern Checker – Parity Check Temperature Sensor Differential Scalable Output: 10 mA to 30 mA 196-Ball, 12-mm × 12-mm NFBGA A high-performance low-jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital quadrature modulator correction (QMC) enables complete IQ compensation for gain, offset and phase between channels in direct upconversion applications. Digital data is input to the device through a 32-bit wide LVDS data bus with on-chip termination. The wide bus allows the processing of high-bandwidth signals. The device includes a FIFO, data pattern checker, and parity test to ease the input interface. The interface also allows ...