DatasheetsPDF.com

RM48L940 Dataheets PDF



Part Number RM48L940
Manufacturers Texas Instruments
Logo Texas Instruments
Description 16- and 32-Bit RISC Flash Microcontroller
Datasheet RM48L940 DatasheetRM48L940 Datasheet (PDF)

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community RM48L940, RM48L740, RM48L540 SPNS175C – APRIL 2012 – REVISED JUNE 2015 RM48Lx40 16- and 32-Bit RISC Flash Microcontroller 1 Device Overview 1.1 Features 1 • High-Performance Microcontroller for SafetyCritical Applications – Dual CPUs Running in Lockstep – ECC on Flash and RAM Interfaces – Built-In Self-Test (BIST) for CPU and On-chip RAMs – Error Signaling Module With Error Pin – Voltage and Clock Monitori.

  RM48L940   RM48L940


Document
Product Folder Sample & Buy Technical Documents Tools & Software Support & Community RM48L940, RM48L740, RM48L540 SPNS175C – APRIL 2012 – REVISED JUNE 2015 RM48Lx40 16- and 32-Bit RISC Flash Microcontroller 1 Device Overview 1.1 Features 1 • High-Performance Microcontroller for SafetyCritical Applications – Dual CPUs Running in Lockstep – ECC on Flash and RAM Interfaces – Built-In Self-Test (BIST) for CPU and On-chip RAMs – Error Signaling Module With Error Pin – Voltage and Clock Monitoring • ARM® Cortex®-R4F 32-Bit RISC CPU – Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline – FPU With Single- and Double-Precision – 12-Region Memory Protection Unit (MPU) – Open Architecture With Third-Party Support • Operating Conditions – System Clock up to 200 MHz – Core Supply Voltage (VCC): 1.2 V Nominal – I/O Supply Voltage (VCCIO): 3.3 V Nominal – ADC Supply Voltage (VCCAD): 3.0 to 5.25 V • Integrated Memory – 3MB of Program Flash With ECC (RM48L940) – 2MB of Program Flash With ECC (RM48L740/540) – 256KB of RAM With ECC (RM48L940/740) – 192KB of RAM With ECC (RM48L540) – 64KB of Flash With ECC for Emulated EEPROM • 16-Bit External Memory Interface • Common Platform Architecture – Consistent Memory Map Across Family – Real-Time Interrupt (RTI) Timer OS Timer – 96-Channel Vectored Interrupt Module (VIM) – 2-Channel Cyclic Redundancy Checker (CRC) • Direct Memory Access (DMA) Controller – 16 Channels and 32 Peripheral Requests – Parity Protection for Control Packet RAM – DMA Accesses Protected by Dedicated MPU • Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In Slip Detector • Separate Nonmodulating PLL • Trace and Calibration Capabilities – Embedded Trace Macrocell (ETM-R4) – Data Modification Module (DMM) – RAM Trace Port (RTP) – Parameter Overlay Module (POM) • Multiple Communication Interfaces – 10/100 Mbps Ethernet MAC (EMAC) • IEEE 802.3 Compliant (3.3-V I/O Only) • Supports MII, RMII, and MDIO – Three CAN Controllers (DCANs) • 64 Mailboxes, Each With Parity Protection • Compliant to CAN Protocol Version 2.0B – Standard Serial Communication Interface (SCI) – Local Interconnect Network (LIN) Interface Controller • Compliant to LIN Protocol Version 2.1 • Can be Configured as a Second SCI – Inter-Integrated Circuit (I2C) – Three Multibuffered Serial Peripheral Interfaces (MibSPIs) • 128 Words With Parity Protection Each – Two Standard Serial Peripheral Interfaces (SPIs) • Two Next Generation High-End Timer (N2HET) Modules – N2HET1: 32 Programmable Channels – N2HET2: 18 Programmable Channels – 160-Word Instruction RAM Each With Parity Protection – Each N2HET Includes Hardware Angle Generator – Dedicated High-End Transfer Unit (HTU) With MPU for Each N2HET • Two 12-Bit Multibuffered ADC Modules – ADC1: 24 Channels – ADC2: 16 Channels Shared With ADC1 – 64 Result Buffers With Parity Protection Each • General-Purpose Input/Output (GPIO) Pins Capable of Generating Interrupts – 16 Pins on the ZWT Package – 10 Pins on the PGE Package • IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight™ Components • JTAG Security Module • Packages – 144-Pin Quad Flatpack (PGE) [Green] – 337-Ball Grid Array (ZWT) [Green] 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. RM48L940, RM48L740, RM48L540 SPNS175C – APRIL 2012 – REVISED JUNE 2015 1.2 Applications • Industrial Safety Applications – Industrial Automation – Safe Programmable Logic Controllers (PLCs) – Power Generation and Distribution – Turbines and Windmills – Elevators and Escalators • Medical Applications – Ventilators – Defibrillators – Infusion and Insulin Pumps – Radiation Therapy – Robotic Surgery www.ti.com 2 Device Overview Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated www.ti.com RM48L940, RM48L740, RM48L540 SPNS175C – APRIL 2012 – REVISED JUNE 2015 1.3 Description The RM48Lx40 device is a high-performance microcontroller family for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os. The RM48Lx40 device integrates the ARM Cortex-R4F Floating-Point CPU. The CPU offers an efficient 1.66 DMIPS/MHz, and has configurations that can run up to 200 MHz, providing up to 332 DMIPS. The device supports the little-endian [LE] format. The RM48L940 device has 3MB of integrated flash and 256KB of data RAM. The RM48L740 device has 2MB of integrated flash and 256KB of data RAM. The RM48L540 device has 2MB of integrated flash and 192KB of data RAM. Both the flash and RAM have single-bit error correction and double-bit error detec.


RM48L530 RM48L940 RM48L740


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)