DC-DC Converter. TPS54540-Q1 Datasheet

TPS54540-Q1 Converter. Datasheet pdf. Equivalent


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TPS54540-Q1
SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015
TPS54540-Q1 4.5-V to 42-V Input, 5-A, Step-Down DC-DC Converter With Eco-mode™
1 Features
1 Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H1C
– Device CDM ESD Classification Level C3B
• High-Efficiency at Light Loads With Pulse-
Skipping Eco-mode™
• 92-mΩ High-Side MOSFET
• 146-μA Operating Quiescent Current and 2-µA
Shutdown Current
• 100-kHz to 2.5-MHz Adjustable Switching
Frequency
• Synchronizes to External Clock
• Low Dropout at Light Loads With Integrated
BOOT Recharge FET
• Adjustable UVLO Voltage and Hysteresis
• 0.8-V 1% Internal Voltage Reference
• 8-Pin HSOP PowerPAD™ Package
• –40°C to 150°C TJ Operating Range
• Supported by WEBENCH® Software Tool
2 Applications
• Vehicle Accessories: GPS (See SLVA412),
Entertainment, ADAS, eCall
• USB-Dedicated Charging Ports and Battery
Chargers (See SLVA464)
• Industrial Automation and Motor Control
• 12-V, 24-V, and 48-V Industrial, Automotive, and
Communications Power Systems
SPACE
Simplified Schematic
VIN VIN BOOT
TPS54540-Q1
EN SW
VOUT
COMP
RT/CLK
FB
GND
3 Description
The TPS54540-Q1 device is a 42-V, 5-A, step-down
regulator with an integrated high-side MOSFET. The
device survives load-dump pulses up to 65 V per ISO
7637. Current mode control provides simple external
compensation and flexible component selection. A
low-ripple pulse-skip mode reduces the no load
supply current to 146 μA. Shutdown supply current is
reduced to 2 μA when the enable pin is pulled low.
Undervoltage lockout is internally set at 4.3 V but can
be increased using an external resistor divider at the
enable pin. The output voltage start-up ramp is
internally controlled to provide a controlled start-up
and eliminate overshoot.
A wide adjustable frequency range allows either
efficiency or external component size to be optimized.
Output current is limited cycle-by-cycle. Frequency
foldback and thermal shutdown protect internal and
external components during an overload condition.
The TPS54540-Q1 is available in an 8-pin thermally-
enhanced HSOP PowerPAD package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS54540-Q1
HSOP (8)
4.89 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Efficiency vs Load Current
100
90
80
70
60
50
40
30
20 VSINe=rie1s21V
10 VSINe=rie3s62V
0 VSINe=rie6s04V
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
IO - Output Current (A)
C024
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


TPS54540-Q1 Datasheet
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Description Step Down DC-DC Converter
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TPS54540-Q1
SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information .................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements ................................................ 5
6.7 Switching Characteristics .......................................... 6
6.8 Typical Characteristics .............................................. 7
7 Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 22
8 Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Applications ................................................ 23
9 Power Supply Recommendations...................... 36
10 Layout................................................................... 37
10.1 Layout Guidelines ................................................. 37
10.2 Layout Example .................................................... 37
10.3 Estimated Circuit Area .......................................... 37
11 Device and Documentation Support ................. 38
11.1 Device Support...................................................... 38
11.2 Documentation Support ........................................ 38
11.3 Community Resources.......................................... 38
11.4 Trademarks ........................................................... 38
11.5 Electrostatic Discharge Caution ............................ 38
11.6 Glossary ................................................................ 38
12 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2013) to Revision B
Page
ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section,
Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
• Changed Thermal Information table values............................................................................................................................ 4
Changes from Original (September 2013) to Revision A
Page
• Changed the Electrostatic Discharge (CDM) Max value From: 500 V To: 750 V .................................................................. 4
• Changed the ELECTRICAL CHARACTERISTICS condition statement From: TJ = –40°C to 150°C, VIN = 4.5 to 60 V
To: TJ = –40°C to 150°C, VIN = 4.5 to 42 V........................................................................................................................... 5
• Changed Figure 4 X-axis From: max = 60V To: max = 45V .................................................................................................. 7
• Changed Figure 16 X-axis From: max = 60V To: max = 45V ................................................................................................ 8
• Changed Figure 18 X-axis From: max = 60V To: max = 45V ................................................................................................ 8
• Changed the FBD, removed the Logic block and Shutdown signal from the OV comparator ............................................. 12
• Changed the APPLICATION INFORMATION section.......................................................................................................... 23
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Product Folder Links: TPS54540-Q1



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5 Pin Configuration and Functions
TPS54540-Q1
SLVSC56B – SEPTEMBER 2013 – REVISED NOVEMBER 2015
DDA Package
8-Pin HSOP With PowerPAD
Top View
BOOT
1
8 SW
VIN 2
7
PowerPAD
9
EN 3
6
GND
COMP
RT/CLK
4
5 FB
Pin Functions
PIN
I/O
NAME
NO.
DESCRIPTION
BOOT
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
1 I minimum required to operate the high side MOSFET, the MOSFET stops switching until the capacitor is
refreshed.
COMP
6
I
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this pin.
EN
3
I
Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
FB 5 I Inverting input of the transconductance (gm) error amplifier.
GND
7 — Ground
RT/CLK
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
4 I a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is
reenabled and the operating mode returns to resistor frequency programming.
SW 8 O The source of the internal high-side power MOSFET and switching node of the converter.
VIN 2 I Input supply voltage is connected to this pin with a 4.5-V to 42-V operating range.
PowerPAD
9 — GND pin must be electrically connected to the exposed pad on the printed-circuit-board for proper operation.
Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: TPS54540-Q1
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