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ICS8432-51 Dataheets PDF



Part Number ICS8432-51
Manufacturers Renesas
Logo Renesas
Description CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Datasheet ICS8432-51 DatasheetICS8432-51 Datasheet (PDF)

700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ICS8432-51 GENERAL DESCRIPTION The ICS8432-51 is a general purpose, dual output Crystal-to3.3V Differential LVPECL High Frequency Synthesizer. The ICS8432-51 has a selectable REF_CLK or crystal input. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or .

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700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ICS8432-51 GENERAL DESCRIPTION The ICS8432-51 is a general purpose, dual output Crystal-to3.3V Differential LVPECL High Frequency Synthesizer. The ICS8432-51 has a selectable REF_CLK or crystal input. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interface to the configuration logic. The low phase noise characteristics of the ICS8432-51 make it an ideal clock source for Gigabit Ethernet, Fibre Channel 1 and 2, and Infiniband applications. FEATURES • Dual differential 3.3V LVPECL outputs • Selectable crystal oscillator interface or LVCMOS/LVTTL REF_CLK • Output frequency range: 31.25MHz to 700MHz • Crystal input frequency range: 12MHz to 25MHz • VCO range: 250MHz to 700MHz • Parallel or serial interface for programming counter and output dividers • RMS period jitter: 3.5ps (maximum) • Cycle-to-cycle jitter: 25ps (maximum) • 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages • Replaces the ICS8432-01 BLOCK DIAGRAM PIN ASSIGNMENT XTAL_IN nP_LOAD VCO_SEL M0 M1 M2 M3 M4 VCO_SEL XTAL_SEL REF_CLK XTAL1 XTAL2 OSC 0 1 MR S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1 PLL PHASE DETECTOR VCO 0 ÷1 ÷2 ÷M ÷4 1 ÷8 CONFIGURATION INTERFACE LOGIC IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER FOUT0 nFOUT0 FOUT1 nFOUT1 TEST 1 32 31 30 29 28 27 26 25 M5 1 M6 2 M7 3 M8 4 N0 5 N1 6 nc 7 ICS8432-51 24 XTAL_OUT 23 REF_CLK 22 XTAL_SEL 21 VCCA 20 S_LOAD 19 S_DATA 18 S_CLOCK VEE 8 17 MR 9 10 11 12 13 14 15 16 VEE nFOUT0 FOUT0 VCCO nFOUT1 FOUT1 VCC TEST 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View ICS8432CY-51 REVISION F NOVEMBER 13, 2012 ICS8432-51 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. The ICS8432-51 features a fully integrated PLL and therefore, requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8432-51 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x M The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 10 ≤ M ≤ 28. The frequency out is defined as follows: FOUT = fVCO = fxtal x M NN Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift reg-ister are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each ris-ing edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. T.


TSR1-48240WI ICS8432-51 IMX185LQJ-C


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