CD74HC73

Data sheet acquired from Harris Semiconductor SCHS134E February 1998 - Revised September 2003 CD54HC73, CD74HC73, CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger [ /Title (CD74 HC73, CD74 HCT73 ) /Subject (Dual J-K FlipFlop Features Description Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times Asynchronous Reset Complementary Outputs Buffered Inputs TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF, Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. These flip-flops have independent J, K, Reset and Clock inputs and Q and Q outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC/HCT107 but differs in terminal assignment and in some parametric limits. The HCT logic family is functionally as well as pin compatible with the standard LS logic family. Ordering Information Significant Power Reduction Compared to LSTTL Logic ICs ...