Phase-Locked Loop. CD74HCT7046A Datasheet

CD74HCT7046A Loop. Datasheet pdf. Equivalent


etcTI CD74HCT7046A
Data sheet acquired from Harris Semiconductor
SCHS218C
February 1998 - Revised October 2003
CD74HC7046A,
CD74HCT7046A
Phase-Locked Loop
with VCO and Lock Detector
[ /Title
(CD74
HC704
6A,
CD74
HCT70
46A)
/Sub-
ject
(Phase-
Locked
Loop
Features
Description
• Center Frequency of 18MHz (Typ) at VCC = 5V,
Minimum Center Frequency of 12MHz at VCC = 4.5V
• Choice of Two Phase Comparators
- Exclusive-OR
- Edge-Triggered JK Flip-Flop
• Excellent VCO Frequency Linearity
• VCO-Inhibit Control for ON/OFF Keying and for Low
Standby Power Consumption
• Minimal Frequency Drift
• Zero Voltage Offset Due to Op-Amp Buffer
• Operating Power-Supply Voltage Range
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Applications
• FM Modulation and Demodulation
• Frequency Synthesis and Multiplication
• Frequency Discrimination
• Tone Decoding
• Data Synchronization and Conditioning
• Voltage-to-Frequency Conversion
• Motor-Speed Control
• Related Literature
- AN8823, CMOS Phase-Locked-Loop Application
Using the CD74HC/HCT7046A and
CD74HC/HCT7046A
The CD74HC7046A and CD74HCT7046A high-speed
silicon-gate CMOS devices, specified in compliance with
JEDEC Standard No. 7A, are phase-locked-loop (PLL)
circuits that contain a linear voltage-controlled oscillator
(VCO), two-phase comparators (PC1, PC2), and a lock
detector. A signal input and a comparator input are common
to each comparator. The lock detector gives a HIGH level at
pin 1 (LD) when the PLL is locked. The lock detector
capacitor must be connected between pin 15 (CLD) and pin
8 (Gnd). For a frequency range of 100kHz to 10MHz, the
lock detector capacitor should be 1000pF to 10pF,
respectively.
The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small
voltage signals within the linear region of the input amplifiers.
With a passive low-pass filter, the 7046A forms a second-
order loop PLL. The excellent VCO linearity is achieved by
the use of linear op-amp techniques.
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD74HC7046AE
-55 to 125
16 Ld PDIP
CD74HC7046AM
-55 to 125
16 Ld SOIC
CD74HC7046AMT
-55 to 125
16 Ld SOIC
CD74HC7046AM96
-55 to 125
16 Ld SOIC
CD74HCT7046AE
-55 to 125
16 Ld PDIP
CD74HCT7046AM
-55 to 125
16 Ld SOIC
CD74HCT7046AMT
-55 to 125
16 Ld SOIC
CD74HCT7046AM96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
0.1


CD74HCT7046A Datasheet
Recommendation CD74HCT7046A Datasheet
Part CD74HCT7046A
Description Phase-Locked Loop
Feature CD74HCT7046A; Data sheet acquired from Harris Semiconductor SCHS218C February 1998 - Revised October 2003 CD74HC7.
Manufacture etcTI
Datasheet
Download CD74HCT7046A Datasheet




etcTI CD74HCT7046A
CD74HC7046A, CD74HCT7046A
Pinout
CD74HC7046A, CD74HCT7046A
(PDIP, SOIC)
TOP VIEW
LD 1
PC1OUT 2
COMPIN 3
VCOOUT 4
INH 5
C1A 6
C1B 7
GND 8
16 VCC
15 CLD
14 SIGIN
13 PC2OUT
12 R2
11 R1
10 DEMOUT
9 VCOIN
Functional Diagram
3
COMPIN
14
SIGIN
φ
C1A
C1B
R1
R2
VCOIN
INH
6
7
11
12
9
5
VCO
2
PC1OUT
15
CLD
13
PC2OUT
1
LD
4
VCOOUT
10
DEMOUT
6
C1A
C1
74
C1B
3 14
COMPIN SIGIN
PC1OUT 2
VREF
12 R2
R2
-
11 R1
R1
VCO
-+
10
R5
-+
INH VCOIN
59
150
1.5K
LOCK DETECTOR
D Q UP
CP Q
RD
VCC
Q
D
CP Q DOWN
RD
LOCK
1
DETECTOR
OUTPUT
15
VCC
p
PC2OUT
13
CLD
LOCK
DETECTOR
CAPACITOR
R3
C2
n
GND
FIGURE 1. LOGIC DIAGRAM
2



etcTI CD74HCT7046A
CD74HC7046A, CD74HCT7046A
Pin Descriptions
PIN NO. SYMBOL
NAME AND FUNCTION
1 LD Lock Detector Output (Active High)
2 PC1OUT Phase Comparator 1 Output
3 COMPIN Comparator Input
4 VCOOUT VCO Output
5 INH Inhibit Input
6 C1A Capacitor C1 Connection A
7 C1B Capacitor C1 Connection B
8 Gnd Ground (0V)
9 VCOIN VCO Input
10 DEMOUT Demodulator Output
11 R1 Resistor R1 Connection
12 R2 Resistor R2 Connection
13 PC2OUT Phase Comparator 2 Output
14 SIGIN Signal Input
15 CLD Lock Detector Capacitor Input
16
VCC
Positive Supply Voltage
General Description
VCO
The VCO requires one external capacitor C1 (between C1A
and C1B) and one external resistor R1 (between R1 and
Gnd) or two external resistors R1 and R2 (between R1 and
Gnd, and R2 and Gnd). Resistor R1 and capacitor C1 deter-
mine the frequency range of the VCO. Resistor R2 enables
the VCO to have a frequency offset if required. See logic dia-
gram, Figure 1.
The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is pro-
vided at pin 10 (DEMOUT). In contrast to conventional tech-
niques where the DEMOUT voltage is one threshold voltage
lower than the VCO input voltage, here the DEMOUT voltage
equals that of the VCO input. If DEMOUT is used, a load
resistor (RS) should be connected from DEMOUT to Gnd; if
unused, DEMOUT should be left open. The VCO output
(VCOOUT) can be connected directly to the comparator
input (COMPIN), or connected via a frequency-divider. The
VCO output signal has a specified duty factor of 50%. A
LOW level at the inhibit input (INH) enables the VCO, while a
HIGH level disables the VCO to minimize standby power
consumption.
Phase Comparators
The signal input (SIGIN) can be directly coupled to the self-
biasing amplifier at pin 14, provided that the signal swing is
between the standard HC family input logic levels, Capaci-
tive coupling is required for signals with smaller swings.
Phase Comparator 1 (PC1)
This is an Exclusive-OR network. The signal and comparator
input frequencies (fi) must have a 50% duty factor to obtain
the maximum locking range. The transfer characteristic of
PC1, assuming ripple (fr = 2fi) is suppressed, is:
VDEMOUT = (VCC/π) (φSIGIN - φCOMPIN) where VDEMOUT
is the demodulator output at pin 10; VDEMOUT = VPC1OUT
(via low-pass filter).
The average output voltage from PC1, fed to the VCO input
via the low-pass filter and seen at the demodulator output at
pin 10 (VDEMOUT), is the resultant of the phase differences
of signals (SIGIN) and the comparator input (COMPIN) as
shown in Figure 2. The average of VDEM is equal to 1/2 VCC
when there is no signal or noise at SIGIN, and with this input
the VCO oscillates at the center frequency (fo). Typical wave-
forms for the PC1 loop locked at fo shown in Figure 3.
The frequency capture range (2fc) is defined as the fre-
quency range of input signals on which the PLL will lock if it
was initially out-of-lock. The frequency lock range (2fL) is
defined as the frequency range of input signals on which the
loop will stay locked if it was initially in lock. The capture
range is smaller or equal to the lock range.
With PC1, the capture range depends on the low-pass filter
characteristics and can be made as large as the lock range.
This configuration retains lock behavior even with very noisy
input signals. Typical of this type of phase comparator is that
it can lock to input frequencies close to the harmonics of the
VCO center frequency.
Phase Comparator 2 (PC2)
This is a positive edge-triggered phase and frequency detec-
tor. When the PLL is using this comparator, the loop is con-
trolled by positive signal transitions and the duty factors of
SIGIN and COMPIN are not important. PC2 comprises two
D-type flip-flops, control-gating and a three-state output
stage. The circuit functions as an up-down counter (Figure
1) where SIGIN causes an up-count and COMPIN a down-
count. The transfer function of PC2, assuming ripple (fr = fi)
is suppressed, is:
VDEMOUT = (VCC/4π) (φSIGN - φCOMPIN) where VDEMOUT
is the demodulator output at pin 10; VDEMOUT = VPC2OUT
(via low-pass filter).
The average output voltage from PC2, fed to the VCO via the
low-pass filter and seen at the demodulator output at pin 10
(VDEMOUT), is the resultant of the phase differences of
SIGIN and COMPIN as shown in Figure 4. Typical waveforms
for the PC2 loop locked at fo are shown in Figure 5.
When the frequencies of SIGIN and COMPIN are equal but
the phase of SIGIN leads that of COMPIN, the p-type output
driver at PC2OUT is held “ON” for a time corresponding to
the phase differences (φDEMOUT). When the phase of SIGIN
lags that of COMPIN, the n-type driver is held “ON”.
When the frequency of SIGIN is higher than that of COMPIN,
the p-type output driver is held “ON” for most of the input sig-
nal cycle time, and for the remainder of the cycle both n-type
and p-type drivers are “OFF” (three-state). If the SIGIN fre-
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