D Flip-Flop. CD74HCT74 Datasheet

CD74HCT74 Flip-Flop. Datasheet pdf. Equivalent


etcTI CD74HCT74
Data sheet acquired from Harris Semiconductor
SCHS124D
January 1998 - Revised September 2003
CD54HC74, CD74HC74,
CD54HCT74, CD74HCT74
Dual D Flip-Flop with Set and Reset
Positive-Edge Trigger
[ /Title
(CD54H
C74,
CD74H
C74,
CD74H
CT74)
/Subject
(Dual D
Flip-
Flop
with Set
Features
Description
• Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times
• Asynchronous Set and Reset
• Complementary Outputs
• Buffered Inputs
• TTAyp=ic2a5lofCMAX = 50MHz at VCC = 5V, CL = 15pF,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
The ’HC74 and ’HCT74 utilize silicon gate CMOS technology
to achieve operating speeds equivalent to LSTTL parts.
They exhibit the low power consumption of standard CMOS
integrated circuits, together with the ability to drive 10 LSTTL
loads.
This flip-flop has independent DATA, SET, RESET and
CLOCK inputs and Q and Q outputs. The logic level present
at the data input is transferred to the output during the
positive-going transition of the clock pulse. SET and RESET
are independent of the clock and are accomplished by a low
level at the appropriate input.
The HCT logic family is functionally as well as pin compatible
with the standard LS logic family.
Ordering Information
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC74F3A
-55 to 125
14 Ld CERDIP
CD54HCT74F3A
-55 to 125
14 Ld CERDIP
CD74HC74E
-55 to 125
14 Ld PDIP
CD74HC74M
-55 to 125
14 Ld SOIC
CD74HC74MT
-55 to 125
14 Ld SOIC
CD74HC74M96
-55 to 125
14 Ld SOIC
CD74HCT74E
-55 to 125
14 Ld PDIP
CD74HCT74M
-55 to 125
14 Ld SOIC
CD74HCT74MT
-55 to 125
14 Ld SOIC
CD74HCT74M96
-55 to 125
14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1


CD74HCT74 Datasheet
Recommendation CD74HCT74 Datasheet
Part CD74HCT74
Description Dual D Flip-Flop
Feature CD74HCT74; Data sheet acquired from Harris Semiconductor SCHS124D January 1998 - Revised September 2003 CD54HC.
Manufacture etcTI
Datasheet
Download CD74HCT74 Datasheet




etcTI CD74HCT74
CD54HC74, CD74HC74, CD54HCT74, CD74HCT74
Pinout
CD54HC74, CD54HCT74
(CERDIP)
CD74HC74, CD74HCT74
(PDIP, SOIC)
TOP VIEW
1R 1
1D 2
1CP 3
1S 4
1Q 5
1Q 6
GND 7
14 VCC
13 2R
12 2D
11 2CP
10 2S
9 2Q
8 2Q
Functional Diagram
1
RESET
DATA
CLOCK
2
3
4
SET
13
RESET
12
DATA
11
CLOCK
10
SET
R
D
F/F 1
CP
S
R
D
F/F 2
CP
S
5
Q
6
Q
9
Q
8
Q
GND = PIN 7
VCC = PIN 14
TRUTH TABLE
INPUTS
OUTPUTS
SET RESET
CP
D
Q
Q
LHXXHL
HLXXLH
L
L
X
X
H (Note 1)
H (Note 1)
HHHH L
HHL LH
H H L X Q0 Q0
H= High Level (Steady State)
L= Low Level (Steady State)
X= Don’t Care
= Low-to-High Transition
Q0 = the level of Q before the indicated input conditions were established.
NOTE:
1. This configuration is nonstable, that is, it will not persist when set and reset inputs return to their inactive (high) level.
2



etcTI CD74HCT74
CD54HC74, CD74HC74, CD54HCT74, CD74HCT74
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 2)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
SYMBOL
TEST
CONDITIONS
25oC
VI (V) IO (mA) VCC (V) MIN TYP MAX
VIH -
-
VIL - -
VOH
VIH or
VIL
-0.02
-
-4
-5.2
VOL VIH or 0.02
VIL
-
4
5.2
II
VCC or
-
GND
2 1.5 - -
4.5 3.15 -
-
6 4.2 - -
2 - - 0.5
4.5 - - 1.35
6 - - 1.8
2 1.9 - -
4.5 4.4 -
-
6 5.9 - -
- ---
4.5 3.98 -
-
6 5.48 -
-
2 - - 0.1
4.5 - - 0.1
6 - - 0.1
- ---
4.5 - - 0.26
6 - - 0.26
6 - - ±0.1
-40oC TO 85oC
MIN MAX
1.5 -
3.15 -
4.2 -
- 0.5
- 1.35
- 1.8
1.9 -
4.4 -
5.9 -
--
3.84 -
5.34 -
- 0.1
- 0.1
- 0.1
--
- 0.33
- 0.33
- ±1
-55oC TO 125oC
MIN MAX UNITS
1.5 - V
3.15 -
V
4.2 - V
- 0.5 V
- 1.35 V
- 1.8 V
1.9 - V
4.4 - V
5.9 - V
- -V
3.7 - V
5.2 - V
- 0.1 V
- 0.1 V
- 0.1 V
- -V
- 0.4 V
- 0.4 V
- ±1 µA
3





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)