CD74HCT74

Data sheet acquired from Harris Semiconductor SCHS124D January 1998 - Revised September 2003 CD54HC74, CD74HC74, CD54HCT74, CD74HCT74 Dual D Flip-Flop with Set and Reset Positive-Edge Trigger [ /Title (CD54H C74, CD74H C74, CD74H CT74) /Subject (Dual D FlipFlop with Set Features Description Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times Asynchronous Set and Reset Complementary Outputs Buffered Inputs TTAyp=ic2a5lofCMAX = 50MHz at VCC = 5V, CL = 15pF, Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times The ’HC74 and ’HCT74 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. This flip-flop has independent DATA, SET, RESET and CLOCK inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive-going transition of the clock pulse. SET and RESET are independent of the clock and are accomplished by a low level at the appropriate input. The HCT logic family is functionally as well as pin compatible with the standard LS logic family. Ordering Information Significant Power Reduction Compared...