Presettable Counters. CD54HCT163 Datasheet

CD54HCT163 Counters. Datasheet pdf. Equivalent


etcTI CD54HCT163
The CD54HCT161 is obsolete
and no longer is supplied.
Data sheet acquired from Harris Semiconductor
SCHS154D
February 1998 - Revised October 2003
CD54/74HC161, CD54/74HCT161,
CD54/74HC163, CD54/74HCT163
High-Speed CMOS Logic
Presettable Counters
[ /Title
(CD74
HC161
,
CD74
HCT16
1,
CD74
HC163
,
CD74
HCT16
3)
/Sub-
ject
(High
Speed
CMOS
Logic
Preset-
table
Counte
rs)
/Autho
r ()
/Key-
words
(High
Speed
CMOS
Logic
Preset-
table
Counte
rs,
High
Speed
Features
• ’HC161, ’HCT161 4-Bit Binary Counter,
Asynchronous Reset
• ’HC163, ’HCT163 4-Bit Binary Counter,
Synchronous Reset
• Synchronous Counting and Loading
• Two Count Enable Inputs for n-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Description
Two count enables, PE and TE, in each counter are
provided for n-bit cascading. In all counters reset action
occurs regardless of the level of the SPE, PE and TE inputs
(and the clock input, CP, in the ’HC161 and ’HCT161
types).
If a decade counter is preset to an illegal state or assumes
an illegal state when power is applied, it will return to the
normal sequence in one count as shown in state diagram.
The look-ahead carry feature simplifies serial cascading of
the counters. Both count enable inputs (PE and TE) must
be high to count. The TE input is gated with the Q outputs
of all four stages so that at the maximum count the terminal
count (TC) output goes high for one clock period. This TC
pulse is used to enable the next cascaded stage.
Ordering Information
PART NUMBER
CD54HC161F3A
CD54HC163F3A
CD54HCT163F3A
CD74HC161E
CD74HC161M
CD74HC161MT
CD74HC161M96
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
The ’HC161, ’HCT161, ’HC163, and ’HCT163 are
presettable synchronous counters that feature look-ahead
carry logic for use in high-speed counting applications. The
’HC161 and ’HCT161 are asynchronous reset decade and
binary counters, respectively; the ’HC163 and ’HCT163
devices are decade and binary counters, respectively, that
are reset synchronously with the clock. Counting and
parallel presetting are both accomplished synchronously
with the negative-to-positive transition of the clock.
A low level on the synchronous parallel enable input, SPE,
disables counting operation and allows data at the P0 to P3
inputs to be loaded into the counter (provided that the
setup and hold requirements for SPE are met).
All counters are reset with a low level on the Master Reset
input, MR. In the ’HC163 and ’HCT163 counters
(synchronous reset types), the requirements for setup and
hold time with respect to the clock must be met.
CD74HC163E
CD74HC163M
CD74HC163MT
CD74HC163M96
CD74HCT161E
CD74HCT161M
CD74HCT161MT
CD74HCT161M96
CD74HCT163E
CD74HCT163M
CD74HCT163MT
CD74HCT163M96
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1


CD54HCT163 Datasheet
Recommendation CD54HCT163 Datasheet
Part CD54HCT163
Description High-Speed CMOS Logic Presettable Counters
Feature CD54HCT163; The CD54HCT161 is obsolete and no longer is supplied. Data sheet acquired from Harris Semiconductor .
Manufacture etcTI
Datasheet
Download CD54HCT163 Datasheet




etcTI CD54HCT163
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
Pinout
CD54HC161, CD54HCT161, CD54HC163, CD54HCT163
(CERDIP)
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
(PDIP, SOIC)
TOP VIEW
MR 1
CP 2
P0 3
P1 4
P2 5
P3 6
PE 7
GND 8
16 VCC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 TE
9 SPE
Functional Diagram
P0 P1 P2 P3
3456
9
SPE
2
CP
1
MR
7
PE
10
TE
14
Q0
13
Q1
12
Q2
11
Q3
15
TC
2



etcTI CD54HCT163
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
OPERATING MODE
Reset (Clear)
Parallel Load
Count
Inhibit
MODE SELECT - FUNCTION TABLE FOR ’HC161 AND ’HCT161
INPUTS
MR CP PE TE SPE Pn
LXXXXX
HXX
l
l
HXX l h
H h h h (Note 3) X
H X I (Note 2) X h (Note 3) X
H X X I (Note 2) h (Note 3) X
OUTPUTS
Qn TC
LL
LL
H (Note 1)
Count
(Note 1)
qn (Note 1)
qn L
MODE SELECT - FUNCTION TABLE FOR ’HC163 AND ’HCT163
INPUTS
OUTPUTS
OPERATING MODE
MR
CP
PE
TE SPE Pn
Qn
TC
Reset (Clear)
l XXXXL L
Parallel Load
h (Note 3)
X
X
l
l
LL
h (Note 3)
X
X
l
h H (Note 1)
Count
h (Note 3)
h
h h (Note 3) X
Count
(Note 1)
Inhibit
h (Note 3) X I (Note 2) X h (Note 3) X
qn (Note 1)
h (Note 3)
X
X I (Note 2) h (Note 3) X
qn
L
H = High voltage level steady state; L = Low voltage level steady state; h = High voltage level one setup time prior to the Low-to-High clock
transition; l = Low voltage level one setup time prior to the Low-to-High clock transition; X = Don’t Care; q = Lower case letters indicate the
state of the referenced output prior to the Low-to-High clock transition; = Low-to-High clock transition.
NOTES:
1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH for HC/HCT161 and ’HC/HCT163).
2. The High-to-Low transition of PE or TE on the ’HC/HCT161 and the ’HC/HCT163 should only occur while CP is HIGH for conventional
operation.
3. The Low-to-High transition of SPE on the ’HC/HCT161 and SPE or MR on the ’HC/HCT163 should only occur while CP is HIGH for
conventional operation.
3







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