Shift Register. CD74HCT165 Datasheet

CD74HCT165 Register. Datasheet pdf. Equivalent


etcTI CD74HCT165
Data sheet acquired from Harris Semiconductor
SCHS156C
February 1998 - Revised October 2003
CD54HC165, CD74HC165,
CD54HCT165, CD74HCT165
High-Speed CMOS Logic
8-Bit Parallel-In/Serial-Out Shift Register
[ /Title
(CD74H
C165,
CD74H
CT165)
/Subject
(High
Speed
CMOS
Logic 8-
Bit Par-
allel-
Features
Description
• Buffered Inputs
• Asynchronous Parallel Load
• Complementary Outputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The ’HC165 and ’HCT165 are 8-bit parallel or serial-in shift
registers with complementary serial outputs (Q7 and Q7)
available from the last stage. When the parallel load (PL)
input is LOW, parallel data from the D0 to D7 inputs are
loaded into the register asynchronously. When the PL is
HIGH, data enters the register serially at the DS input and
shifts one place to the right (Q0Q1Q2, etc.) with each
positive-going clock transition. This feature allows parallel-
to-serial converter expansion by typing the Q7 output to the
DS input of the succeeding device.
For predictable operation the LOW-to-HIGH transition of CE
should only take place while CP is HIGH. Also, CP an d CE
should be LOW before the LOW-to-HIGH transition of PL to
prevent shifting the data when PL goes HIGH.
Ordering Information
PART NUMBER
CD54HC165F3A
CD54HCT165F3A
CD74HC165E
TEMP. RANGE
(oC)
PACKAGE
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld PDIP
Pinout
CD54HC165, CD54HCT165
(CERDIP)
CD74HC165, CD74HCT165
(PDIP, SOIC)
TOP VIEW
PL 1
CP 2
D4 3
D5 4
D6 5
D7 6
Q7 7
GND 8
16 VCC
15 CE
14 D3
13 D2
12 D1
11 D0
10 DS
9 Q7
CD74HC165M
-55 to 125
16 Ld SOIC
CD74HC165MT
-55 to 125
16 Ld SOIC
CD54HC165M96
-55 to 125
16 Ld SOIC
CD74HCT165E
-55 to 125
16 Ld PDIP
CD74HCT165M
-55 to 125
16 Ld SOIC
CD74HCT165MT
-55 to 125
16 Ld SOIC
CD54HCT165M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1


CD74HCT165 Datasheet
Recommendation CD74HCT165 Datasheet
Part CD74HCT165
Description 8-Bit Parallel-In/Serial-Out Shift Register
Feature CD74HCT165; Data sheet acquired from Harris Semiconductor SCHS156C February 1998 - Revised October 2003 CD54HC1.
Manufacture etcTI
Datasheet
Download CD74HCT165 Datasheet




etcTI CD74HCT165
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
Functional Diagram
PARALLEL
DATA
INPUTS
11
D0
12
D1
13
D2
14
D3
3
D4
4
D5
5
D6
6
D7
DS 10
9
Q7
7
Q7
SERIAL
OUTPUTS
PL
CE
CP
1 15 2
GND = 8
VCC = 16
TRUTH TABLE
INPUTS
OPERATING MODE
PL CE CP DS D0 - D7
Parallel Load
LXXXL
L XXXH
Serial Shift
HLl X
HLhX
Hold Do Nothing
HHXXX
H =High Voltage Level
h = High Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition
l = Low Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition
L = Low Voltage Level
X = Don’t Care
= Transition from Low to High Level
qn = Lower Case Letters Indicate The State Of the Reference Output Clock Transition
Qn REGISTER
Q0 Q1 - Q6
L L-L
H H-H
L q0 - q5
H q0 - q5
q0 q1 - q6
OUTPUTS
Q7 Q7
LH
HL
q6 q6
q6 q6
q7 q7
2



etcTI CD74HCT165
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current per Output, IO
For VO < -0.5V VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
SYMBOL
TEST
CONDITIONS
25oC
VI (V) IO (mA) VCC (V) MIN TYP MAX
VIH -
-
VIL - -
VOH
VOL
II
VIH or
VIL
-0.02
-0.02
-0.02
-4
-5.2
VIH or
VIL
0.02
0.02
0.02
4
5.2
VCC or
GND
-
2 1.5 - -
4.5 3.15 -
-
6 4.2 - -
2 - - 0.5
4.5 - - 1.35
6 - - 1.8
2 1.9 - -
4.5 4.4 -
-
6 5.9 - -
4.5 3.98 -
-
6 5.48 -
-
2 - - 0.1
4.5 - - 0.1
6 - - 0.1
4.5 - - 0.26
6 - - 0.26
6 - - ±0.1
-40oC TO 85oC
MIN MAX
1.5 -
3.15 -
4.2 -
- 0.5
- 1.35
- 1.8
1.9 -
4.4 -
5.9 -
3.84 -
5.34 -
- 0.1
- 0.1
- 0.1
- 0.33
- 0.33
- ±1
-55oC TO 125oC
MIN MAX UNITS
1.5 -
3.15 -
4.2 -
- 0.5
- 1.35
- 1.8
1.9 -
4.4 -
5.9 -
3.7 -
5.2 -
V
V
V
V
V
V
V
V
V
V
V
- 0.1 V
- 0.1 V
- 0.1 V
- 0.4 V
- 0.4 V
- ±1 µA
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