D-Type Flip-Flop. CD54HC173 Datasheet

CD54HC173 Flip-Flop. Datasheet pdf. Equivalent


etcTI CD54HC173
Data sheet acquired from Harris Semiconductor
SCHS158E
February 1998 - Revised October 2003
CD54HC173, CD74HC173,
CD54HCT173, CD74HCT173
High-Speed CMOS Logic
Quad D-Type Flip-Flop, Three-State
[ /Title
(CD74H
C173,
CD74H
CT173)
/Subject
(High
Speed
CMOS
Logic
Quad D-
Type
Features
• Three-State Buffered Outputs
• Gated Input and Output Enables
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Pinout
Description
The ’HC173 and ’HCT173 high speed three-state quad D-
type flip-flops are fabricated with silicon gate CMOS technol-
ogy. They possess the low power consumption of standard
CMOS Integrated circuits, and can operate at speeds com-
parable to the equivalent low power Schottky devices. The
buffered outputs can drive 15 LSTTL loads. The large output
drive capability and three-state feature make these parts ide-
ally suited for interfacing with bus lines in bus oriented sys-
tems.
The four D-type flip-flops operate synchronously from a com-
mon clock. The outputs are in the three-state mode when
either of the two output disable pins are at the logic “1” level.
The input ENABLES allow the flip-flops to remain in their
present states without having to disrupt the clock If either of
the 2 input ENABLES are taken to a logic “1” level, the Q
outputs are fed back to the inputs, forcing the flip-flops to
remain in the same state. Reset is enabled by taking the
MASTER RESET (MR) input to a logic “1” level. The data
outputs change state on the positive going edge of the clock.
The ’HCT173 logic family is functionally, as well as pin com-
patible with the standard LS logic family.
Ordering Information
CD54HC173, CD54HCT173
(CERDIP)
CD74HC173
(PDIP, SOIC, SOP, TSSOP)
CD74HCT173
(PDIP, SOIC)
TOP VIEW
OE 1
OE2 2
Q0 3
Q1 4
Q2 5
Q3 6
CP 7
GND 8
16 VCC
15 MR
14 D0
13 D1
12 D2
11 D3
10 E2
9 E1
PART NUMBER
CD54HC173F3A
CD54HCT173F3A
CD74HC173E
CD74HC173M
CD74HC173MT
CD74HC173M96
CD74HC173NSR
CD74HC173PW
CD74HC173PWR
CD74HC173PWT
TEMP. RANGE
(oC)
PACKAGE
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld PDIP
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOP
-55 to 125
16 Ld TSSOP
-55 to 125
16 Ld TSSOP
-55 to 125
16 Ld TSSOP
CD74HCT173E
-55 to 125
16 Ld PDIP
CD74HCT173M
-55 to 125
16 Ld SOIC
CD74HCT173MT
-55 to 125
16 Ld SOIC
CD74HCT173M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1


CD54HC173 Datasheet
Recommendation CD54HC173 Datasheet
Part CD54HC173
Description Quad D-Type Flip-Flop
Feature CD54HC173; Data sheet acquired from Harris Semiconductor SCHS158E February 1998 - Revised October 2003 CD54HC1.
Manufacture etcTI
Datasheet
Download CD54HC173 Datasheet




etcTI CD54HC173
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
Functional Diagram
E1
E2
14
D0
13
D1
12
D2
11
D3
7
CP
10 9
15 1 2
MR
OE1
OE2
3
Q0
4
Q1
5
Q2
6
Q3
TRUTH TABLE
INPUTS
DATA ENABLE DATA OUTPUT
MR CP E1 E2 D Qn
HXXXX L
L L X X X Q0
L H X X Q0
L X H X Q0
LLLLL
L L LHH
H= High Voltage Level
L = Low Voltage Level
X= Irrelevant
= Transition from Low to High Level
Q0= Level Before the Indicated Steady-State Input Conditions Were
Established
NOTE:
1. When either OE1 or OE2 (or both) is (are) high, the output is dis-
abled to the high-impedance state, however, sequential opera-
tion of the flip-flops is not affected.
2



etcTI CD54HC173
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
Logic Diagram
9
E1
10
E2
14
D0
7
CP
15
MR
1
OE1
2
OE2
13
D1
12
D2
11
D3
DQ
CP Q
R
VCC
P
3
Q0
N
3 CIRCUITS IDENTICAL TO ABOVE CIRCUIT
IN DASHED ENCLOSURE
4
Q1
5
Q2
6
Q3
3







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