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CD74HCT174 Dataheets PDF



Part Number CD74HCT174
Manufacturers Texas Instruments
Logo Texas Instruments
Description Hex D-Type Flip-Flop
Datasheet CD74HCT174 DatasheetCD74HCT174 Datasheet (PDF)

Data sheet acquired from Harris Semiconductor SCHS159C August 1997 - Revised October 2003 CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 High-Speed CMOS Logic Hex D-Type Flip-Flop with Reset [ /Title (CD74 HC174 , CD74 HCT17 4) /Subject (High Speed CMOS Logic Hex DType FlipFlop Features • Buffered Positive Edge Triggered Clock • Asynchronous Common Reset • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . ..

  CD74HCT174   CD74HCT174



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Data sheet acquired from Harris Semiconductor SCHS159C August 1997 - Revised October 2003 CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 High-Speed CMOS Logic Hex D-Type Flip-Flop with Reset [ /Title (CD74 HC174 , CD74 HCT17 4) /Subject (High Speed CMOS Logic Hex DType FlipFlop Features • Buffered Positive Edge Triggered Clock • Asynchronous Common Reset • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Description The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flipflops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six masterslave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174. Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC174F3A -55 to 125 16 Ld CERDIP CD54HCT174F3A -55 to 125 16 Ld CERDIP CD74HC174E -55 to 125 16 Ld PDIP CD74HC174M -55 to 125 16 Ld SOIC CD74HC174MT -55 to 125 16 Ld SOIC CD74HC174M96 -55 to 125 16 Ld SOIC CD74HCT174E -55 to 125 16 Ld PDIP CD74HCT174M -55 to 125 16 Ld SOIC CD74HCT174MT -55 to 125 16 Ld SOIC CD74HCT174M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC174, CD54HCT174 (CERDIP) CD74HC174, CD74HCT174 (PDIP, SOIC) TOP VIEW MR 1 Q0 2 D0 3 D1 4 Q1 5 D2 6 Q2 7 GND 8 16 VCC 15 Q5 14 D5 13 D4 12 Q4 11 D3 10 Q3 9 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 Functional Diagram CP D0 CP D Q0 R D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 MR Q5 TRUTH TABLE INPUTS OUTPUT RESET (MR) L CLOCK CP X DATA Dn X Qn L H ↑ HH H ↑ LL H L X Q0 H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, ↑ = Transition from Low to High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established Logic Diagram 3 (4, 6, 11, 13, 14) D Dn CL p n CL 1 MR 9 CP R CL p n CL CL p n CL CL CP ONE OF SI.


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