Up/Down Counters. CD74HCT191 Datasheet

CD74HCT191 Counters. Datasheet pdf. Equivalent


etcTI CD74HCT191
CD54HC190, CD74HC190
CD54HC191, CD74HC191, CD54HCT191, CD74HCT191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
D 2-V to 6-V VCC Operation (’HC190, 191)
D 4.5-V to 5.5-V VCC Operation (’HCT191)
D Wide Operating Temperature Range of
−55°C to 125°C
D Synchronous Counting and Asynchronous
Loading
D Two Outputs for n-Bit Cascading
D Look-Ahead Carry for High-Speed Counting
D Balanced Propagation Delays and
Transition Times
D Standard Outputs Drive Up To 15 LS-TTL
Loads
D Significant Power Reduction Compared to
LS-TTL Logic ICs
CD54HC190, 191; CD54HCT191 . . . F PACKAGE
CD74HC190 . . . E, NS, OR PW PACKAGE
CD74HC191, CD74HCT191 . . . E OR M PACKAGE
(TOP VIEW)
B
QB
QA
CTEN
D/U
QC
QD
GND
1
2
3
4
5
6
7
8
16 VCC
15 A
14 CLK
13 RCO
12 MAX/MIN
11 LOAD
10 C
9D
description/ordering information
The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and
CD54/74HCT191 are asynchronously presettable binary counters.
Presetting the counter to the number on preset data inputs (A−D) is accomplished by a low asynchronous
parallel load (LOAD) input. Counting occurs when LOAD is high, count enable (CTEN) is low, and the down/up
(D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented
synchronously with the low-to-high transition of the clock.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
CD74HC190E
CD74HC190E
PDIP − E
Tube of 25
CD74HC191E
CD74HCT191E
CD74HC191E
CD74HCT191E
Tube of 40
CD74HC191M
SOIC − M
Reel of 2500
Reel of 250
CD74HC191M96
CD74HC191MT
HC191M
−55°C to 125°C SOP − NS
Tube of 40
Reel of 2000
CD74HCT191M
CD74HC190NSR
HCT191M
HC190M
Tube of 90
CD74HC190PW
TSSOP − PW Reel of 2000
Reel of 250
CD74HC190PWR HJ190
CD74HC190PWT
CD54HC190F3A CD54HC190F3A
CDIP − F
Tube of 25
CD54HC191F3A CD54HC191F3A
CD54HCT191F3A CD54HCT191F3A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1


CD74HCT191 Datasheet
Recommendation CD74HCT191 Datasheet
Part CD74HCT191
Description Synchronous Up/Down Counters
Feature CD74HCT191; CD54HC190, CD74HC190 CD54HC191, CD74HC191, CD54HCT191, CD74HCT191 SYNCHRONOUS UP/DOWN COUNTERS WITH .
Manufacture etcTI
Datasheet
Download CD74HCT191 Datasheet




etcTI CD74HCT191
CD54HC190, CD74HC190
CD54HC191, CD74HC191, CD54HCT191, CD74HCT191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
description/ordering information (continued)
When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes
high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading
(see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO) output, which normally is high, goes
low, and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO
(see Figure 2).
If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to
the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).
LOAD
FUNCTION TABLE
INPUTS
CTEN
D/U
CLK
FUNCTION
HL L
Count up
HLH
Count down
LXX
HHX
X Asynchronous preset
X No change
D/U or CTEN should be changed only when clock is high.
X = Don’t care
Low-to-high clock transition
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265



etcTI CD74HCT191
CD54HC190, CD74HC190
CD54HC191, CD74HC191, CD54HCT191, CD74HCT191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
’HC190 logic diagram
A
15
B
1
14
CLK
5
D/U
11
LOAD
b
c
d
e
f
g
h
i
LOAD
DATA
TQ
CLKQ
FF0
LOAD
DATA
TQ
CLKQ
FF1
j
4
CTEN
3
QA
2
QB
k
l
m
n
o
p
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3







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