CD54HCT193

CD54/74HC192, CD54/74HC193, CD54/74HCT193 Data sheet acquired from Harris Semiconductor SCHS163F High-Speed CMOS Logic September 1997 - Revised October 2003 Presettable Synchronous 4-Bit Up/Down Counters [ /Title (CD74 HC192 , CD74 HC193 , CD74 HCT19 3) /Subject (High Speed CMOS Logic Preset- Features Synchronous Counting and Asynchronous Loading Two Outputs for N-Bit Cascading Look-Ahead Carry for High-Speed Counting Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Description The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively. Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL). The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the ClockDown input) and decremented on the low to high transition of the Clock-Down input (and a high level on t...