Shift Register. CD54HC194 Datasheet

CD54HC194 Register. Datasheet pdf. Equivalent


etcTI CD54HC194
Data sheet acquired from Harris Semiconductor
SCHS164G
September 1997 - Revised May 2006
CD54HC194, CD74HC194,
CD74HCT194
High-Speed CMOS Logic
4-Bit Bidirectional Universal Shift Register
[ /Title
(CD74
HC194,
CD74H
CT194)
/Sub-
ject
(High-
Speed
CMOS
Logic
4-Bit
Features
Description
• Four Operating Modes
- Shift Right, Shift Left, Hold and Reset
• Synchronous Parallel or Serial Operation
• TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF,
• Asynchronous Master Reset
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The ’HC194 and CD74HCT194 are 4-bit shift registers with
Asynchronous Master Reset (MR). In the parallel mode (S0
and S1 are high), data is loaded into the associated flip-flop
and appears at the output after the positive transition of the
clock input (CP). During parallel loading serial data flow is
inhibited. Shift left and shift right are accomplished
synchronously on the positive clock edge with serial data
entered at the shift left (DSL) serial input for the shift left
mode, and at the shift right (DSR) serial input for the shift
right mode. Clearing the register is accomplished by a Low
applied to the Master Reset (MR) pin.
Ordering Information
PART NUMBER
CD54HC194F3A
CD74HC194E
CD74HC194M
CD74HC194MT
CD74HC194M96
CD74HC194NSR
CD74HC194PW
CD74HC194PWR
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
Pinout
CD54HC194 (CERDIP)
CD74HC194 (PDIP, SOIC, SOP, TSSOP)
CD74HCT194 (PDIP)
TOP VIEW
CD74HC194PWT
-55 to 125
16 Ld TSSOP
CD74HCT194E
-55 to 125
16 Ld PDIP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
MR 1
DSR 2
D0 3
D1 4
D2 5
D3 6
DSL 7
GND 8
16 VCC
15 Q0
14 Q1
13 Q2
12 Q3
11 CP
10 S1
9 S0
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2006, Texas Instruments Incorporated
1


CD54HC194 Datasheet
Recommendation CD54HC194 Datasheet
Part CD54HC194
Description 4-Bit Bidirectional Universal Shift Register
Feature CD54HC194; Data sheet acquired from Harris Semiconductor SCHS164G September 1997 - Revised May 2006 CD54HC194,.
Manufacture etcTI
Datasheet
Download CD54HC194 Datasheet




etcTI CD54HC194
CD54HC194, CD74HC194, CD74HCT194
Functional Diagram
3
D0
4
D1
5
D2
6
D3
DSL
DSR
S0
S1
MR
CP
72
15
Q0
14
Q1
13
Q2
12
Q3
9 10 1 11
GND = 8
VCC = 16
TRUTH TABLE
OPERATING
MODE
Reset (Clear)
CP MR
XL
INPUTS
OUTPUT
S1
S0
DSR DSL
Dn
Q0
Q1
Q2
Q3
X X XXXL L L L
Hold (Do Nothing)
X
H
l
l X X X q0 q1 q2 q3
Shift Left
H
h
l X l X q1 q2 q3 L
H
h
l X h X q1 q2 q3 H
Shift Right
H
l
h l X X L q0 q1 q2
H
l
h h X X H q0 q1 q2
Parallel Load
H
h
h X X dn d0 d1 d2 d3
H = High Voltage Level,
h = High Voltage Level One Set-up Time Prior To The Low to High Clock Transition,
L = Low Voltage Level,
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition,
dn (qn) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low To High Clock
Transition,
X = Don’t Care,
= Transition from Low to High Level
2



etcTI CD54HC194
CD54HC194, CD74HC194, CD74HCT194
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Package Thermal Impedance, θJA (see Note 2):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
25oC
-40oC TO 85oC -55oC TO 125oC
PARAMETER
HC TYPES
SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
High Level Input
Voltage
VIH -
- 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 -
- 3.15
- 3.15 -
V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage
VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5
-
- 1.35
-
1.35
-
1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH
VIH or -0.02
2
1.9 -
-
1.9
-
1.9
-
V
VIL
-0.02 4.5 4.4 - - 4.4
- 4.4
-V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
-4
4.5 3.98 -
- 3.84
-
3.7
-
V
-5.2
6 5.48 -
- 5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
VOL VIH or 0.02
2
- - 0.1 -
0.1
-
0.1 V
VIL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6
- - 0.1 -
0.1
-
0.1 V
Low Level Output
Voltage
TTL Loads
4
4.5
-
- 0.26
-
0.33
-
5.2
6
-
- 0.26
-
0.33
-
0.4 V
0.4 V
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