CD74HC195

Data sheet acquired from Harris Semiconductor SCHS165E September 1997 - Revised October 2003 CD54HC195, CD74HC195 High-Speed CMOS Logic 4-Bit Parallel Access Register [ /Title (CD74 HC195 ) /Subject (High Speed CMOS Logic 4-Bit Parallel Access Register) /Autho Features Description Asynchronous Master Reset J, K, (D) Inputs to First Stage Fully Synchronous Serial or Parallel Data Transfer Shift Right and Parallel Load Capability Complementary Output From Last Stage Buffered Inputs CTyLp=ic1a5l pfMF,ATXA==5205MoHCz at VCC = 5V, Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V PInout CD54HC195 (CERDIP) CD74HC195 (PDIP, SOIC, SOP, TSSOP) TOP VIEW MR 1 J2 K3 D0 4 D1 5 D2 6 D3 7 GND 8 16 VCC 15 Q0 14 Q1 13 Q2 12 Q3 11 Q3 10 CP 9 PE The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The two modes of operation, shift right (Q0-Q1) and parallel load, are controlled by the state of the Parallel Enable (PE) input. Serial data enters the first flip-flop (Q0) via th...