CD54HC162

CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS D Synchronous Counting and Loading D Two Count-Enable Inputs for n-Bit Cascading D Asynchronous Reset (CD54HC160) D Synchronous Reset (CD54HC162) D Look-Ahead Carry for High-Speed Counting D Operating Range 2-V to 6-V VCC D EPIC™ (Enhanced-Performance Implanted CMOS) Process D Packaged in Ceramic (F) DIPs SCHS301 – JUNE 2000 CD54HC160, CD54HC162 . . . F PACKAGE (TOP VIEW) CLR CLK A B C D ENP GND 1 2 3 4 5 6 7 8 16 VCC 15 RCO 14 QA 13 QB 12 QC 11 QD 10 ENT 9 LOAD description These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The CD54HC160 and CD54HC162 are BCD decade counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The...