DECADE COUNTERS. CD54HC162 Datasheet

CD54HC162 COUNTERS. Datasheet pdf. Equivalent


etcTI CD54HC162
CD54HC160, CD54HC162
BCD SYNCHRONOUS DECADE COUNTERS
D Synchronous Counting and Loading
D Two Count-Enable Inputs for n-Bit
Cascading
D Asynchronous Reset (CD54HC160)
D Synchronous Reset (CD54HC162)
D Look-Ahead Carry for High-Speed Counting
D Operating Range 2-V to 6-V VCC
D EPIC(Enhanced-Performance Implanted
CMOS) Process
D Packaged in Ceramic (F) DIPs
SCHS301 – JUNE 2000
CD54HC160, CD54HC162 . . . F PACKAGE
(TOP VIEW)
CLR
CLK
A
B
C
D
ENP
GND
1
2
3
4
5
6
7
8
16 VCC
15 RCO
14 QA
13 QB
12 QC
11 QD
10 ENT
9 LOAD
description
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed
counting designs. The CD54HC160 and CD54HC162 are BCD decade counters. Synchronous operation is
provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other
when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation
eliminates the output counting spikes that are normally associated with synchronous (ripple-clock) counters.
A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
These counters are fully programmable; that is, they can be preset to any number between 0 and 9. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the CD54HC160 is asynchronous. A low level at the clear (CLR) input sets all four of the
flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 with QA high). This high-level overflow ripple-carry pulse can
be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level
of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The CD54HC160 and CD54HC162 are supplied in 16-lead hermetic dual-in-line ceramic packages (F suffix),
and are characterized for operation over the full military temperature range of –55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1


CD54HC162 Datasheet
Recommendation CD54HC162 Datasheet
Part CD54HC162
Description BCD SYNCHRONOUS DECADE COUNTERS
Feature CD54HC162; CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS D Synchronous Counting and Loading D Two Count.
Manufacture etcTI
Datasheet
Download CD54HC162 Datasheet




etcTI CD54HC162
CD54HC160, CD54HC162
BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 – JUNE 2000
logic symbol
CLR
LOAD
1
9
ENT
ENP
CLK
A
B
C
D
10
7
2
3
4
5
6
CD54HC160 BINARY COUNTER
WITH DIRECT CLEAR
CTRDIV10
CT=0
M1
M2 3CT=9
G3
G4
C5/2,3,4+
1,5D [1]
[2]
[4]
[8]
15
RCO
14
QA
13
QB
12
QC
11
QD
CLR
LOAD
1
9
ENT
ENP
CLK
A
B
C
D
10
7
2
3
4
5
6
CD54HC162 BINARY COUNTER
WITH SYNCHRONOUS CLEAR
CTRDIV10
5CT=0
M1
M2 3CT=9
G3
G4
C5/2,3,4+
1,5D [1]
[2]
[4]
[8]
15
RCO
14
QA
13
QB
12
QC
11
QD
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265



etcTI CD54HC162
CD54HC160 logic diagram (positive logic)
CLR
LOAD
ENT
ENP
1
9
10
7
CLK 2
A3
CD54HC160, CD54HC162
BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 – JUNE 2000
15 RCO
C1
1D
R
14 QA
B4
C5
C1
1D
R
13
QB
C1
1D
R
12 QC
D6
CD54HC162 decade counter is similar; however, the clear is synchronous.
C1
1D
R
11 QD
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3





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