SN74LV244AT Octal Buffers/Drivers Datasheet

SN74LV244AT Datasheet, PDF, Equivalent


Part Number

SN74LV244AT

Description

Octal Buffers/Drivers

Manufacture

etcTI

Total Page 21 Pages
Datasheet
Download SN74LV244AT Datasheet


SN74LV244AT
www.ti.com
FEATURES
Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V VCC Operation
Typical tpd = 5.4 ns at 5 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 5 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 5 V, TA = 25°C
Supports Mixed-Mode Voltage Operation on
All Ports
DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 2OE
18 1Y1
17 2A4
16 1Y2
15 2A3
14 1Y3
13 2A2
12 1Y4
11 2A1
SN74LV244AT
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES572C – JUNE 2004 – REVISED AUGUST 2005
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
RGY PACKAGE
(TOP VIEW)
1A1 2
2Y4 3
1A2 4
2Y3 5
1A3 6
2Y2 7
1A4 8
2Y1 9
1
10
20
19 2OE
18 1Y1
17 2A4
16 1Y2
15 2A3
14 1Y3
13 2A2
12 1Y4
11
DESCRIPTION/ORDERING INFORMATION
This octal buffer/driver is designed specifically to improve both the performance and density of 3-state
memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
The SN74LV244AT is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When
OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
TA
–40°C to 85°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
QFN – RGY
Reel of 1000
SN74LV244ATRGYR
SOIC – DW
Tube of 25
Reel of 2000
SN74LV244ATDW
SN74LV244ATDWR
SOP – NS
Reel of 2000
SN74LV244ATNSR
SSOP – DB
Reel of 2000
SN74LV244ATDBR
Tube of 70
SN74LV244ATPW
TSSOP – PW
Reel of 2000
SN74LV244ATPWR
Reel of 250
SN74LV244ATPWT
TVSOP – DGV
Reel of 2000
SN74LV244ATDGVR
TOP-SIDE MARKING
VV244
LV244AT
74LV244AT
LV244AT
LV244AT
LV244AT
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated

SN74LV244AT
SN74LV244AT
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES572C – JUNE 2004 – REVISED AUGUST 2005
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
1
1OE
1A1 2
FUNCTION TABLE
(EACH 4-BIT BUFFER/DRIVER)
INPUTS
OE A
LH
LL
HX
OUTPUT
Y
H
L
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
19
2OE
18 1Y1
2A1 11
9 2Y1
1A2 4
16 1Y2
2A2 13
7 2Y2
1A3 6
14 1Y3
2A3 15
5 2Y3
1A4 8
12 1Y4
2A4 17
3 2Y4
2


Features www.ti.com FEATURES • Inputs Are TTL-V oltage Compatible • 4.5-V to 5.5-V VC C Operation • Typical tpd = 5.4 ns at 5 V • Typical VOLP (Output Ground Bo unce) <0.8 V at VCC = 5 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 5 V, TA = 25°C • Su pports Mixed-Mode Voltage Operation on All Ports DB, DGV, DW, NS, OR PW PACKA GE (TOP VIEW) 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 2OE 18 1Y1 17 2A4 16 1Y2 15 2 A3 14 1Y3 13 2A2 12 1Y4 11 2A1 SN74LV2 44AT OCTAL BUFFER/DRIVER WITH 3-STATE O UTPUTS SCES572C – JUNE 2004 – REVIS ED AUGUST 2005 • Ioff Supports Partia l-Power-Down Mode Operation • Latch-U p Performance Exceeds 250 mA Per JESD 1 7 • ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) RGY PACKAG E (TOP VIEW) 1OE VCC 1A1 2 2Y4 3 1A2 4 2Y3 5 1A3 6 2Y2 7 1A4 8 2Y1 9 1 10 20 19 2OE 18 1Y1 17 2A4 16 1Y2 15 2A3 14 1Y3 13 2A2 12 1Y4 11 GND 2A1 DESCRIPTION/ORDERING .
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