SN74LV245AT Bus Transceivers Datasheet

SN74LV245AT Datasheet, PDF, Equivalent


Part Number

SN74LV245AT

Description

Octal Bus Transceivers

Manufacture

etcTI

Total Page 26 Pages
Datasheet
Download SN74LV245AT Datasheet


SN74LV245AT
SN74LV245AT
www.ti.com
SCLS605D – DECEMBER 2004 – REVISED JULY 2013
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
Check for Samples: SN74LV245AT
FEATURES
1
• Inputs Are TTL-Voltage Compatible
• 4.5-V to 5.5-V VCC Operation
• Typical tpd of 3.5 ns at 5 V
• Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 5 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) >2.3 V
at VCC = 5 V, TA = 25°C
• Supports Mixed-Mode Voltage Operation on
All Ports
• Ioff Supports Partial-Power-Down Mode
Operation
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION
This octal bus transceiver is designed for
asynchronous two-way communication between data
buses. The control-function implementation minimizes
external timing requirements.
The SN74LV245AT allows data transmission from the
A bus to the B bus or from the B bus to the A bus,
depending on the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be
used to disable the device so that the buses are
effectively isolated.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 OE
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 B8
RGY PACKAGE
(TOP VIEW)
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
1
10
20
19 OE
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated

SN74LV245AT
SN74LV245AT
SCLS605D – DECEMBER 2004 – REVISED JULY 2013
FUNCTION TABLE
(EACH TRANSCEIVER)
INPUTS
OE DIR
OPERATION
L L B data to A bus
L H A data to B bus
HX
Isolation
LOGIC DIAGRAM (POSITIVE LOGIC)
1
DIR
19
OE
A1 2
18
B1
To Seven Other Channels
www.ti.com
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Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: SN74LV245AT


Features SN74LV245AT www.ti.com SCLS605D – DE CEMBER 2004 – REVISED JULY 2013 OCTA L BUS TRANSCEIVER WITH 3-STATE OUTPUTS Check for Samples: SN74LV245AT FEATURE S 1 • Inputs Are TTL-Voltage Compatib le • 4.5-V to 5.5-V VCC Operation • Typical tpd of 3.5 ns at 5 V • Typic al VOLP (Output Ground Bounce) <0.8 V a t VCC = 5 V, TA = 25°C • Typical VOH V (Output VOH Undershoot) >2.3 V at VCC = 5 V, TA = 25°C • Supports Mixed-M ode Voltage Operation on All Ports • Ioff Supports Partial-Power-Down Mode O peration • Latch-Up Performance Excee ds 250 mA Per JESD 17 • ESD Protectio n Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Devi ce Model (C101) DESCRIPTION This octal bus transceiver is designed for asynch ronous two-way communication between da ta buses. The control-function implemen tation minimizes external timing requir ements. The SN74LV245AT allows data tra nsmission from the A bus to the B bus o r from the B bus to the A bus, depending on the logic level at the direction-control (DIR) .
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