SN54LV20A NAND GATE Datasheet

SN54LV20A Datasheet, PDF, Equivalent


Part Number

SN54LV20A

Description

DUAL 4-INPUT POSITIVE NAND GATE

Manufacture

etcTI

Total Page 17 Pages
Datasheet
Download SN54LV20A Datasheet


SN54LV20A
SN54LV20A, SN74LV20A
DUAL 4ĆINPUT POSITIVEĆNAND GATE
D 2-V to 5.5-V VCC Operation
D Max tpd of 6 ns at 5 V
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D Ioff Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SCES339E − SEPTEMBER 2000 − REVISED APRIL 2005
SN54LV20A . . . J OR W PACKAGE
SN74LV20A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1A
1B
NC
1C
1D
1Y
GND
1
2
3
4
5
6
7
14 VCC
13 2D
12 2C
11 NC
10 2B
9 2A
8 2Y
SN54LV20A . . . FK PACKAGE
(TOP VIEW)
description/ordering information
These dual 4-input positive-NAND gates are
designed for 2-V to 5.5-V VCC operation.
The ’LV20A devices perform the Boolean function
Y = A B C D or Y = A + B + C + D in positive
logic.
These devices are fully specified for
partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs, preventing
damaging current backflow through the devices
when they are powered down.
NC
3 2 1 20 19
4 18
2C
NC 5
17 NC
1C 6
16 NC
NC 7
15 NC
1D 8
14 2B
9 10 11 12 13
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − D
Tube of 50
Reel of 2500
SN74LV20AD
SN74LV20ADR
LV20A
SOP − NS
Reel of 2000 SN74LV20ANSR
74LV20A
SSOP − DB
−40°C to 85°C
Reel of 2000
Tube of 90
SN74LV20ADBR
SN74LV20APW
LV20A
TSSOP − PW
Reel of 2000 SN74LV20APWR
LV20A
Reel of 250 SN74LV20APWT
TVSOP − DGV Reel of 2000 SN74LV20ADGVR
LV20A
CDIP − J
Tube of 25
SNJ54LV20AJ
SNJ54LV20AJ
−55°C to 125°C CFP − W
Tube of 150 SNJ54LV20AW
SNJ54LV20AW
LCCC − FK
Tube of 55
SNJ54LV20AFK
SNJ54LV20AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2005, Texas Instruments Incorporated
1

SN54LV20A
SN54LV20A, SN74LV20A
DUAL 4ĆINPUT POSITIVEĆNAND GATE
SCES339E − SEPTEMBER 2000 − REVISED APRIL 2005
A
H
L
X
X
X
FUNCTION TABLE
(each gate)
INPUTS
BC
OUTPUT
DY
HHH
L
XXX
H
LXX
H
XLX
H
XXL
H
logic diagram (positive logic)
1A
1B
1C
1D
1
2
4
5
6 1Y
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
2A
2B
2C
2D
9
10
12
13
8 2Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range applied in power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features SN54LV20A, SN74LV20A DUAL 4ĆINPUT POSIT IVEĆNAND GATE D 2-V to 5.5-V VCC Oper ation D Max tpd of 6 ns at 5 V D Typica l VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C D Ioff Supports Par tial-Power-Down Mode Operation D Latch- Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds J ESD 22 − 2000-V Human-Body Model (A11 4-A) − 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) SCES339E − SEPTEMBER 2000 − REVISED APRIL 2005 SN54LV20A . . . J OR W PACK AGE SN74LV20A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) 1A 1B NC 1C 1D 1 Y GND 1 2 3 4 5 6 7 14 VCC 13 2D 12 2 C 11 NC 10 2B 9 2A 8 2Y SN54LV20A . . . FK PACKAGE (TOP VIEW) 1Y 1B GND 1A N C NC 2Y VCC 2A 2D description/ordering information These dual 4-input positiv e-NAND gates are designed for 2-V to 5. 5-V VCC operation. The ’LV20A devices perform the Boolean function Y = A • B • C • D or Y = A + B + C + D in positiv.
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