SN54LV10A POSITIVE-NAND GATE Datasheet

SN54LV10A Datasheet, PDF, Equivalent


Part Number

SN54LV10A

Description

TRIPLE 3-INPUT POSITIVE-NAND GATE

Manufacture

etcTI

Total Page 15 Pages
Datasheet
Download SN54LV10A Datasheet


SN54LV10A
SN54LV10A, SN74LV10A
TRIPLE 3ĆINPUT POSITIVEĆNAND GATE
D 2-V to 5.5-V VCC Operation
D Max tpd of 7 ns at 5 V
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D Ioff Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SCES338E − SEPTEMBER 2000 − REVISED APRIL 2005
SN54LV10A . . . J OR W PACKAGE
SN74LV10A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1A
1B
2A
2B
2C
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 1C
12 1Y
11 3C
10 3B
9 3A
8 3Y
SN54LV10A . . . FK PACKAGE
(TOP VIEW)
description/ordering information
These triple 3-input positive-NAND gates are
designed for 2-V to 5.5-V VCC operation.
The ’LV10A devices perform the Boolean function
Y = A B C or Y = A + B + C in positive logic.
These devices are fully specified for
partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs, preventing
damaging current backflow through the devices
when they are powered down.
2A
3 2 1 20 19
4 18
1Y
NC 5
17 NC
2B 6
16 3C
NC 7
15 NC
2C 8
14 3B
9 10 11 12 13
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − D
Tube of 50
Reel of 2500
SN74LV10AD
SN74LV10ADR
LV10A
SOP − NS
Reel of 2000 SN74LV10ANSR
74LV10A
SSOP − DB
−40°C to 85°C
Reel of 2000
Tube of 90
SN74LV10ADBR
SN74LV10APW
LV10A
TSSOP − PW
Reel of 2000 SN74LV10APWR
LV10A
Reel of 250 SN74LV10APWT
TVSOP − DGV Reel of 2000 SN74LV10ADGVR
LV10A
CDIP − J
Tube of 25
SNJ54LV10AJ
SNJ54LV10AJ
−55°C to 125°C CFP − W
Tube of 150 SNJ54LV10AW
SNJ54LV10AW
LCCC − FK
Tube of 55
SNJ54LV10AFK
SNJ54LV10AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2005, Texas Instruments Incorporated
1

SN54LV10A
SN54LV10A, SN74LV10A
TRIPLE 3ĆINPUT POSITIVEĆNAND GATE
SCES338E − SEPTEMBER 2000 − REVISED APRIL 2005
FUNCTION TABLE
(each gate)
INPUTS
ABC
OUTPUT
Y
HHH
L
LXX
H
XLX
H
XXL
H
logic diagram, each gate (positive logic)
A
B
C
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range applied in power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features SN54LV10A, SN74LV10A TRIPLE 3ĆINPUT POS ITIVEĆNAND GATE D 2-V to 5.5-V VCC Op eration D Max tpd of 7 ns at 5 V D Typi cal VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Typical VO HV (Output VOH Undershoot) >2.3 V at VC C = 3.3 V, TA = 25°C D Ioff Supports P artial-Power-Down Mode Operation D Latc h-Up Performance Exceeds 100 mA Per JES D 78, Class II D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A 114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) SCES338E − SEPTEMBER 2000 − REVIS ED APRIL 2005 SN54LV10A . . . J OR W PA CKAGE SN74LV10A . . . D, DB, DGV, NS, O R PW PACKAGE (TOP VIEW) 1A 1B 2A 2B 2C 2Y GND 1 2 3 4 5 6 7 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y SN54LV10A . . . FK PACKAGE (TOP VIEW) 3A 1C VCC NC NC GND 1A 2Y 1B description/order ing information These triple 3-input po sitive-NAND gates are designed for 2-V to 5.5-V VCC operation. The ’LV10A de vices perform the Boolean function Y = A • B • C or Y = A + B + C in positive l.
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